LTC3736-2 Linear Technology, LTC3736-2 Datasheet - Page 22

• Manufacturer Part Number: LTC3736-2
• Description: Synchronous Controller
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC3736-2
loads. If forced continuous mode is selected and the duty
cycle falls below the minimum on-time requirement, the
output will be regulated by overvoltage protection.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3736-2 circuits: 1) LTC3736-2 DC bias
current, 2) MOSFET gate charge current, 3) I
and 4) transition losses.
1) The V
2) MOSFET gate charge current results from switching the
3) I
22
Efficiency = 100% – (L1 + L2 + L3 + …)
the electrical characteristics, excluding MOSFET driver
currents. V
creases with V
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE
The resulting dQ/dt is a current out of SENSE
typically much larger than the DC supply current. In
continuous mode, I
MOSFETs and inductor. In continuous mode, the aver-
age output current flows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET R
by duty cycle can be summed with the resistance of L
to obtain I
2
R losses are calculated from the DC resistances of the
IN
(pin) current is the DC supply current, given in
2
R losses.
IN
current results in a small loss that in-
IN
U
.
GATECHG
U
= f • Q
W
P
.
DS(ON)
+
s multiplied
U
to ground.
2
+
R losses,
, which is
4) Transition losses apply to the top external P-channel
Other losses, including C
losses and inductor core losses, generally account for less
than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to (∆I
resistance of C
charge C
regulator loop then returns V
During this recovery time, V
overshoot or ringing. OPTI-LOOP
the transient response to be optimized over a wide range
of output capacitance and ESR values.
The I
the dominant pole-zero loop compensation. The I
nal components shown in the Typical Application on the
front page of this data sheet will provide an adequate
starting point for most applications. The values can be
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and I
overall loop stability. The gain of the loop will be increased
by increasing R
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
MOSFET and increase with higher operating frequen-
cies and input voltages. Transition losses can be esti-
mated from:
Transition Loss = 2 (V
TH
series R
OUT
LOAD
, which generates a feedback error signal. The
TH
OUT
pin waveforms that will give a sense of the
C
C
)(ESR), where ESR is the effective series
, and the bandwidth of the loop will be
-C
. ∆I
C
OUT
filter (see Functional Diagram) sets
LOAD
immediately shifts by an amount
IN
IN
)
also begins to charge or dis-
2
I
OUT
O(MAX)
and C
OUT
to its steady-state value.
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®
can be monitored for
compensation allows
C
OUT
RSS
ESR dissipative
(f)
TH
exter-
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