LTC3722-2 Linear Technology, LTC3722-2 Datasheet - Page 14

• Manufacturer Part Number: LTC3722-2
• Description: Synchronous Dual Mode Phase Modulated Full Bridge Controllers
• Manufacturer: Linear Technology

LTC3722-1/LTC3722-2
OPERATIO
LTC3722-1/LTC3722-2 Adaptive Delay Circuitry
The LTC3722-1/LTC3722-2 monitors both the input sup-
ply and instantaneous bridge leg voltages, and commands
a switching transition when the expected zero voltage
condition is reached. DirectSense technology provides
optimal turn-on delay timing, regardless of input voltage,
output load, or component tolerances. The DirectSense
technique requires only a simple voltage divider sense
network to implement. If there is not enough energy to
fully commutate the bridge leg to a ZVS condition, the
LTC3722-1/LTC3722-2 automatically overrides the
DirectSense circuitry and forces a transition. The override
or default delay time is programmed with a resistor from
DPRG to V
Adaptive Mode
The LTC3722-1/LTC3722-2 are configured for adaptive
delay sensing with three pins, ADLY, PDLY and SBUS.
ADLY and PDLY sense the active and passive delay legs
respectively via a voltage divider network as shown in
Figure 2.
The threshold voltage on PDLY and ADLY for both the
rising and falling transitions is set by the voltage on SBUS.
A buffered version of this voltage is used as the threshold
level for the internal DirectSense circuitry. At nominal V
the voltage on SBUS is set to 1.5V by an external voltage
divider between V
proportional to V
DirectSense circuitry uses this characteristic to zero
voltage switch all of the external power MOSFETs, inde-
pendent of input voltage.
14
SBUS
PDLY
REF
R2
R1
1k
.
IN
R3
1k
U
Figure 2. Adaptive Mode
R5
and GND, making this voltage directly
IN
. The LTC3722-1/LTC3722-2
V
IN
A
B
R
CS
D
C
R6
1922 F02
R4
1k
ADLY
IN
,
ADLY and PDLY are connected through voltage dividers to
the active and passive bridge legs respectively. The lower
resistor in the divider is set to 1k. The upper resistor in the
divider is selected for the desired positive transition trip
threshold.
To set up the ADLY and PDLY resistors, first determine at
what drain to source voltage to turn-on the MOSFETs.
Finite delays exist between the time at which the LTC3722-
1/LTC3722-2 controller output transitions, to the time at
which the power MOSFET switches on due to MOSFET
turn on delay and external driver circuit delay. Ideally, we
want the power MOSFET to switch at the instant there is
zero volts across it. By setting a threshold voltage for
ADLY and PDLY corresponding to several volts across the
MOSFET, the LTC3722-1/LTC3722-2 can “anticipate” a
zero voltage VDS and signal the external driver and switch
to turn-on. The amount of anticipation can be tailored for
any application by modifying the upper divider resistor(s).
The LTC3722-1/LTC3722-2 DirectSense circuitry sources
a trimmed current out of PDLY and ADLY after a low to
high level transition occurs. This provides hysteresis and
noise immunity for the PDLY and ADLY circuitry, and sets
the high to low threshold on ADLY or PDLY to nearly the
same level as the low to high threshold, thereby making
the upper and lower MOSFET VDS switch points virtually
identical, independent of V
Example: V
1. Set up SBUS: 1.5V is desired on SBUS with V
2. Set up ADLY and PDLY: 7V of “anticipation” is desired
Set divider current to 100 A.
R1 = 1.5V/100 A = 15k.
R2 = (48V – 1.5V)/100 A = 465k.
An optional small capacitor (0.001 F) can be added
across R1 to decouple noise from this input.
in this circuit to account for the delays of the external
MOSFET driver and gate drive components.
R3, R4 = 1k, sets a nominal 1.5mA in the divider
chain at the threshold.
R5, R6 = (48V – 7V – 1.5V)/1.5mA = 26.3k,
use (2) equal 13k segments.
IN
= 48V nominal (36V to 72V)
IN
.
www.DataSheet4U.com
IN
= 48V.
372212i