LTC3703-5 Linear Technology, LTC3703-5 Datasheet - Page 28

• Manufacturer Part Number: LTC3703-5
• Description: 60V Synchronous Switching Regulator Controller
• Manufacturer: Linear Technology

LTC3703-5
APPLICATIO S I FOR ATIO
estimated at maximum input voltage, assuming a junction
temperature of 100 C (30 C above an ambient of 70 C):
And double check the assumed T
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period in
short circuit) as the top MOSFET, use two Si7850DP
MOSFETs on the bottom:
Next, set the current limit resistor. Since I
limit should be set such that the minimum current limit is
>10A. Minimum current limit occurs at maximum R
Using the above calculation for bottom MOSFET T
max R
Therefore, I
= 0.165V. The R
0.165V/12 A = 14k .
C
(I
OSCON capacitors (18m
output voltage changes due to inductor current ripple and
load steps. The ripple voltage will be:
28
P
MAIN
IN
MAX
T
T
= 36mV
P
J
J
SYNC
is chosen for an RMS current rating of about 5A
V
/2) at 85 C. For the output capacitor, two low ESR
= 70 C + (1.43W)(20 C/W) = 99 C
= 70 C + (1.34W)(20 C/W) = 97 C
OUT(RIPPLE)
DS(ON)
( )
0 67
12
60
60
.
MAX
( )
2
0 022
10 1 0 007 100 25 0 022
W
60 12
= (22m /2) [1 + 0.007 (97-25)] = 16.5m
.
2
10
pin voltage should be set to (10A)(0.0165)
60
2
2
SET
= I
0 76
( )(
.
U
2 200
resistor can now be chosen to be
L(MAX)
( )
W
1 34
.
10 1 0 007 100 25
.
U
2
pF
(
1 43
W
each) are used to minimize
(ESR) = (4A)(0.018 /2)
.
) •
W
–
J
.
10 3 8
in the MOSFET:
W
– .
) ( .
1
(
MAX
–
3 8
)
1
.
= 10A, the
U
) •
(
DS(ON)
250
J
, the
k
)
.
However, a 0A to 10A load step will cause an output
voltage change of up to:
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703-5. These items are also illustrated graphically in
the layout diagram of Figure 20. For layout of a Boost Mode
Converter, layout is similar with V
Check the following in your layout:
1. Keep the signal and power grounds separate. The signal
ground consists of the LTC3703-5 GND pin, the ground
return of C
ground consists of the Schottky diode anode, the source
of the bottom side MOSFET, and the (–) terminal of the
input capacitor and DRV
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal of
the output capacitor as close as possible to the (–)
terminals of the input and DRV
the Schottky loop described in (2).
2. The high di/dt loop formed by the top N-channel
MOSFET, the bottom MOSFET and the C
should have short leads and PC trace lengths to minimize
high frequency noise and voltage stress from inductive
ringing.
3. Connect the drain of the top side MOSFET directly to the
(+) plate of C
MOSFET directly to the (–) terminal of C
provides the AC current to the MOSFETs.
4. Place the ceramic C
diately next to the IC, between DRV
capacitor carries the MOSFET drivers’ current peaks.
Likewise the C
between BOOST and SW.
= 90mV
V
OUT(STEP)
VCC
IN
, and the (–) terminal of V
, and connect the source of the bottom side
B
= I
capacitor should also be next to the IC
LOAD(ESR)
DRVCC
CC
capacitor. Connect the signal
decoupling capacitor imme-
= (10A)(0.009 )
CC
capacitor and away from
www.DataSheet4U.com
IN
CC
and V
and BGRTN. This
IN
OUT
. This capacitor
OUT
IN
. The power
swapped.
capacitor
37035f