LTC2923 Linear Technology, LTC2923 Datasheet - Page 15

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LTC2923

Manufacturer Part Number
LTC2923
Description
Power Supply Tracking Controller
Manufacturer
Linear Technology
Datasheet

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APPLICATIO S I FOR ATIO
Supply Sequencing Example
In Figure 16, the slave 1 supply and the slave 2 supply are
sequenced instead of tracking. The 3.3V supply ramps up
at 100V/s with an external FET and serves as the master
signal. The 1.8V slave 1 supply ramps up at 1000V/s
beginning 10ms after the master signal starts to ramp up.
The 2.5V slave 2 supply ramps up at 1000V/s beginning
25ms after the master signal begins to ramp up. Note that
not every combination of ramp rates and delays is pos-
sible. Small delays and large ratios of slave ramp rate to
master ramp rate may result in solutions that require
negative resistors. In such cases, either the delay must be
increased or the ratio of slave ramp rate to master ramp
rate must be reduced. In this example, solving for the
slave 1 supply yields:
1. Set the ramp rate of the master signal.
2. Solve for the pair of resistors that provide the desired
From Equation 1:
slave supply behavior, assuming no delay.
From Equation 2:
C
R
GATE
TB
=
16 5
=
100
.
1V/DIV
10
k
µ
V s
U
A
/
1000
100
=
100
U
V s
V s
/
nF
/
=
1 65
W
10ms/DIV
.
Figure 16. Supply Sequencing (from Figure 17)
k
U
2923 F16a
MASTER
SLAVE2
SLAVE1
3. Choose R
1.65k
3.48k
3.3V
R
R
TB1
TA1
From Equation 3:
From Equation 4:
From Equation 5:
R
R
R
R
138k
R
100k
88.7k
36.5k
R
R
TA
ONB
ONA
TA
TA
TB2
TA2
′ =
′′ =
= – 2.13kΩ||1.32kΩ = 3.48kΩ
0.1µF
Figure 17. Supply Sequencing Example
TA
1 235
16 5
ON
V
10
0 8
RAMPBUF
TRACK1
TRACK2
CC
.
to obtain the desired delay.
.
.
ms
10ms/DIV
V
10Ω
k
LTC2923
V
• .
GATE
GND
Q1
1 65
100
+
C
100nF
GATE
35 7
1 235
k
0 8
.
V s
RAMP
.
.
/
FB2
FB1
k
V
=
V
1 32
3.3V
MASTER
www.DataSheet4U.com
.
R
35.7k
R
412k
2923 F16b
FA1
FA2
1 65
FB = 1.235V OUT
FB = 0.8V
0 8
.
k
.
R
1V/DIV
DC/DC
DC/DC
FB1
LTC2923
3.3V
3.3V
k
V
R
887k
IN
IN
FB2
16.5k
OUT
=
– .
2 13
2923 F17
15
1.8V
SLAVE1
2.5V
SLAVE2
k
2923fa

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