LTC2498 Linear Technology, LTC2498 Datasheet - Page 16

• Manufacturer Part Number: LTC2498
• Description: 24-Bit 8-/16-Channel ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
LTC2498
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indica-
tor (SIG). If the selected input (V
than 0V, this bit is HIGH. If V
Bit 28 (fourth output bit) is the most signifi cant bit (MSB)
of the result. This bit in conjunction with Bit 29 also pro-
vides underrange and overrange indication. If both Bit 29
and Bit 28 are HIGH, the differential input voltage is above
+FS. If both Bit 29 and Bit 28 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2498 Status Bits
Input Range
V
0V ≤ V
–0.5 • V
V
Bits 28 to 5 are the 24-bit conversion result MSB fi rst.
Bit 5 is the least signifi cant bit (LSB
Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to
0 may be included in averaging or discarded without loss
of resolution.
16
(EXTERNAL)
IN
IN
≥ 0.5 • V
< –0.5 • V
IN
SDO
SCK
SDI
REF
CS
< 0.5 • V
CONVERSION
≤ V
REF
DON'T CARE
REF
IN
Hi-Z
< 0V
REF
SLEEP
Figure 3. Channel Selection, Confi guration Selection and Data Output Timing
Bit 31
EOC
BIT 31
1
EOC
0
0
0
0
1
IN
< 0, this bit is LOW.
BIT 30
“0”
IN
0
2
Bit 30
DMY
= IN
BIT 29
0
0
0
0
24
SIG
EN
3
).
+
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
– IN
MSB
SGL
4
Bit 29
SIG
1
1
0
0
–
ODD
) is greater
5
Bit 28
A2
MSB
6
1
0
1
0
DATA INPUT/OUTPUT
A1
7
A0
8
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must fi rst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the fi rst
rising edge of SCK. Bit 30 is shifted out of the device on
the fi rst falling edge of SCK. The fi nal data bit (Bit 0) is
shifted out on the on the falling edge of the 31st SCK and
may be latched on the rising edge of the 32nd SCK pulse.
On the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN
between –0.3V and V
erating range) a conversion result is generated for any
differential input voltage V
+FS = 0.5 • V
than +FS, the conversion result is clamped to the value
corresponding to +FS + 1LSB. For differential input volt-
ages below –FS, the conversion result is clamped to the
value –FS – 1LSB.
EN2
9
IM
10
FA
11
REF
. For differential input voltages greater
FB
12
CC
SPD
13
+ 0.3V (absolute maximum op-
BIT 18 BIT 17
IN
14
DON'T CARE
from –FS = –0.5 • V
+
and IN
BIT 0
–
32
pins remains
CONVERSION
Hi-Z
REF
2498 F03
2498fc
to