LTC2400 Linear Technology, LTC2400 Datasheet - Page 13

• Manufacturer Part Number: LTC2400
• Description: 24-Bit uPower No Latency ADC in SO-8
• Manufacturer: Linear Technology

APPLICATIONS
The selection of 50Hz or 60Hz rejection can also be made
by driving F
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2400 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the F
frequency f
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods t
While operating with an external conversion clock of a
frequency f
normal mode rejection in a frequency range f
function of the input frequency deviation from f
is shown in Figure 4.
Whenever an external clock is not present at the F
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2400
Table 3. LTC2400 State Duration
State
CONVERT
SLEEP
DATA OUTPUT
4% and its harmonics. The normal mode rejection as a
EOSC
EOSC
O
HEO
O
to an appropriate logic level. A selection
pin and turns off the internal oscillator. The
, the LTC2400 provides better than 110dB
Operating Mode
Internal Oscillator
External Oscillator
Internal Serial Clock
External Serial Clock with
Frequency f
of the external signal must be at least
and t
U
LEO
INFORMATION
SCK
U
are observed.
kHz
W
F
(60Hz Rejection)
F
(50Hz Rejection)
F
with Frequency f
(f
F
(Internal Oscillator)
F
Frequency f
O
O
O
O
O
EOSC
= LOW
= HIGH
= External Oscillator
= LOW/HIGH
= External Oscillator with
EOSC
EOSC
/2560 Rejection)
U
O
pin, the
EOSC
/2560
/2560
EOSC
kHz
kHz
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state as a
function of F
Figure 4. LTC2400 Normal Mode Rejection When
Using an External Oscillator of Frequency f
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
Duration
133ms
160ms
20480/f
As Long As CS = HIGH Until CS = 0 and SCK
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 256/f
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 32/f
(32 SCK cycles)
–100
–110
–120
–130
–140
–60
–70
–80
–90
–12
O
.
EOSC
–8
s
–4
0
4
8
2400 G25
LTC2400
12
EOSC
SCK
EOSC
ms
13
ms