LTC2238 Linear, LTC2238 Datasheet - Page 19

• Manufacturer Part Number: LTC2238
• Description: (LTC2236 - LTC2238) LOW POWER 3V ADC
• Manufacturer: Linear

APPLICATIO S I FOR ATIO
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 0.6dB. See the Typical Performance Charac-
teristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low-jitter squaring circuit before the CLK pin (see
Figure 11).
The noise performance of the LTC2238/LTC2237/LTC2236
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
SINUSOIDAL
Figure 11. Sinusoidal Single-Ended CLK Drive
CLOCK
INPUT
50Ω
4.7µF
0.1µF
U
1k
1k
U
NC7SVU04
FERRITE
0.1µF
BEAD
W
CLK
SUPPLY
CLEAN
LTC2238
LTC2237
LTC2236
223876 F11
U
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
The transformer shown in the example may be terminated
with the appropriate termination for the signaling in use.
The use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed to
ground through a capacitor close to the ADC if the differ-
ential signals originate on a different plane. The use of a
capacitor at the input may result in peaking, and depend-
ing on transmission line length may require a 10Ω to 20Ω
ohm series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
LTC2238/LTC2237/LTC2236
Figure 13. LVDS or PECL CLK Drive Using a Transformer
DIFFERENTIAL
CLOCK
INPUT
100Ω
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
4.7µF
ETC1-1T
5pF-30pF
FERRITE
BEAD
0.1µF
0.1µF
CLK
SUPPLY
CLK
CLEAN
FERRITE
LTC2238/
LTC2237/
BEAD
LTC2236
LTC2238/
LTC2237/
LTC2236
223876 F12
223876 F13
V
CM
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