LTC2209 Linear Technology Corporation, LTC2209 Datasheet - Page 23

• Manufacturer Part Number: LTC2209
• Description: 160Msps ADC
• Manufacturer: Linear Technology Corporation

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APPLICATIONS INFORMATION
output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
Lower OV
from the digital outputs.
Digital Output Buffers (LVDS Modes)
Figure 12 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT
vice versa, which creates a ±350mV differential voltage
across the 100Ω termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output volt-
age to 1.20V. For proper operation each LVDS output pair
must be terminated with an external 100Ω termination
LATCH
FROM
DATA
Figure 11. Equivalent Circuit for a Digital Output Buffer
PREDRIVER
LOGIC
DD
V
DD
voltages will also help reduce interference
LATCH
LTC2209
FROM
DATA
V
DD
PREDRIVER
LOGIC
V
DD
OV
Figure 12. Equivalent Output Buffer in LVDS Mode
DD
LTC2209
+
2209 F11
to OUT
OV
OGND
10k
1.20V
DD
TYPICAL
DATA
OUTPUT
V
0.5V
TO 3.6V
0.1µF
–
DD
or
+
–
3.5mA
10k
resistor, even if the signal is not used (such as OF
CLKOUT
traces for each LVDS output pair should be routed close
together. To minimize clock skew all LVDS PC board traces
should have about the same length.
In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100Ω termination resistor. The output com-
mon mode voltage is 1.20V, the same as standard LVDS
Mode.
Data Format
The LTC2209 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3V
external resistor divider can be user to set the 1/3V
and 2/3V
for the MODE pin.
Table 2. MODE Pin Function
0(GND)
1/3V
2/3V
MODE
V
OV
OV
DD
+
DD
DD
DD
DD
DD
/CLKOUT
43Ω
43Ω
logic levels. Table 2 shows the logic states
2209 F12
100Ω
OGND
–
). To minimize noise the PC board
2’s Complement
2’s Complement
Output Format
Offset Binary
Offset Binary
RECEIVER
OV
3.3V
0.1µF
LVDS
DD
DD
, 2/3V
LTC2209
DD
Cycle Stabilizer
and V
Clock Duty
Off
On
On
Off
+
23
/OF
DD
. An
–
2209f
DD
or