LTC2205 Linear Technology, LTC2205 Datasheet - Page 25

• Manufacturer Part Number: LTC2205
• Description: (LTC2204 / LTC2205) 65Msps/40Msps
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2205 is 65Msps.
The maximum encode rate for the LTC2204 is 40Msps.
For the ADC to operate properly the encode signal should
have a 50% (±2.5%) duty cycle. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
V
THRESHOLD
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
= 1.6V
0.1µF
1.6V
ENC
ENC
+
–
LTC2205/
LTC2204
22054 F09
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3V
The lower limit of the LTC2205/LTC2204 sample rate is
determined by droop of the sample and hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specifi ed minimum operating
frequency for the LTC2205/LTC2204 is 1Msps.
Figure 10. ENC Drive Using a CMOS to PECL Translator
MC100LVELT22
D0
DD
LTC2205/LTC2204
3.3V
or 2/3V
Q0
Q0
130Ω
83Ω
DD
3.3V
using external resistors.
130Ω
83Ω
ENC
ENC
+
–
LTC2205/
LTC2204
22054 F10
25
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