LTC1955 Linear Technology, LTC1955 Datasheet - Page 14

• Manufacturer Part Number: LTC1955
• Description: Dual Smart Card Interface
• Manufacturer: Linear Technology

LTC1955
APPLICATIO S I FOR ATIO
10kV ESD Protection
All smart card pins (CLK A/CLK B, RST A/RST B, I/O A/
I/O B, C4A, C8A and V
of human body model ESD in-situ. In order to ensure
proper ESD protection, careful board layout is required.
The PGND and SGND pins should be tied directly to a
ground plane. The V
very close to the V
the ground plane.
Capacitor Selection
Warning: A polarized capacitor such as tantalum or alumi-
num should never be used for the flying capacitor since its
voltage can reverse upon start up of the LTC1955. Low
ESR ceramic capacitors should always be used for the
flying capacitor.
A total of six capacitors are required to operate the
LTC1955. An input bypass capacitor is required at PV
SV
on each of the smart card V
flying capacitor is required from C
storage capacitor is required on the charge pump out pin
CPO.
To prevent excessive noise spikes due to charge pump
operation, low ESR (equivalent series resistance) multi-
layer ceramic capacitors are strongly recommended.
There are several types of ceramic capacitors available
each having considerably different characteristics. For
example, X7R/X5R ceramic capacitors have excellent volt-
age and temperature stability but relatively low packing
density. Y5V ceramic capacitors have apparently higher
packing density but poor performance over their rated
voltage or temperature ranges. Under certain voltage and
temperature conditions, Y5V and X7R/X5R ceramic ca-
pacitors can be compared directly by case size rather than
specified value for a desired minimum capacitance.
Placement of the capacitors is critical for correct operation
of the LTC1955. Because the charge pump generates large
current steps, all of the capacitors should be placed as
close to the LTC1955 as possible. The low impedance
nature of multilayer ceramic chip capacitors will minimize
voltage spikes but only if the power path is kept very short
14
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BATT
and DV
CC
. Output bypass capacitors are required
CCA
CCA
U
CCA
/V
/V
CCB
CCB
/V
U
CCA
CCB
pins and tied immediately to
capacitors should be located
/V
) can withstand over 10kV
CCB
+
W
pins. A charge pump
to C
–
and a charge
U
BATT
,
(i.e., minimum inductance). The PV
should be especially well bypassed. The capacitor for this
node should be directly adjacent to the QFN package. The
C
LTC1955 can tolerate more distance between the LDO
capacitors and the V
Figure 4 shows an example of a tight printed circuit board
using single layer copper. For best performance a multi-
layer board can be used and should employ a solid ground
plane on at least one layer.
The following capacitors are recommended for use with
the LTC1955:
C
CPO
C
V
CDV
IN
FLY
CCA/B
PO
CC
and flying capacitors should be very close as well. The
V
Type
Figure 4. Optimum Single Layer PCB Layout
X5R
X5R
X5R
CCA
Value
4.7 F
0.1 F
1 F
GND
CCA/B
Case Size
pins.
0805
0603
0402
V
BATT
Murata P/N
GRM40-034 X5R 475K 6.3
GRM39 X5R 105K 6.3
GRM36 X5R 104K 10
V
BATT
CCB
/SV
1955 F04
BATT
sn1955 1955fs
nodes