LTC1662 Linear Technology, LTC1662 Datasheet - Page 7

• Manufacturer Part Number: LTC1662
• Description: Ultralow Power/ Dual 10-Bit DAC in MSOP
• Manufacturer: Linear Technology

OPERATIO
Transfer Function
The transfer function for the LTC1662 is:
where k is the decimal equivalent of the binary DAC input
code D9-D0 and V
Power-On Reset
The LTC1662 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range
–0.3V
Ratings). Particular care should be taken during power
supply turn-on and turn-off sequences, when the voltage
at V
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Control code, the 10-bit Input code and two don’t-care bits.
Table 1. LTC1662 Input Word
After the Input word is loaded into the register (see Figure 1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide Input code data path is then buffered
by two latch registers.
The first of these, the Input Register, is used for loading new
input codes. The second buffer, the DAC Register, is used
for updating the DAC outputs. Each DAC has its own 10-bit
Input Register and 10-bit DAC Register.
By selecting the appropriate 4-bit Control code (see Table 2)
it is possible to perform single operations, such as loading
one DAC or changing Power-Down status (Sleep/Wake).
A3 A2 A1
Control Code
V
CC
OUT IDEAL
(Pin 6) is in transition.
(
V
REF
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
)
U
V
REF
1024
CC
k
is the voltage at REF (Pin 6).
+ 0.3V (see Absolute Maximum
Input Word
V
Input Code
REF
D0
X1 X0
Don’t
Care
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part up.
The DACs can be loaded separately or together, but the
outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the D
is shifted into the 16-bit Shift Register on the positive edge
of SCK. The 4-bit Control code, A3-A0, is loaded first, then
the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last.
When the full 16-bit Input word has been shifted in, CS/LD
is pulled high, causing the system to respond according to
Table 2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110
instruction (see Table 2). In this mode, the digital circuits
remain active while the analog sections are disabled; static
power consumption is greatly reduced. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
Sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110
ignored).
To save instruction cycles, the DACs may be prepared with
new input codes during Sleep (control codes 0001
0010
to wake the part and to update the output values.
Alternatively, one DAC may be loaded with a new input
code during Sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
For example, control code 0001
during Sleep. Then Control code 0101
wakes the part and simultaneously updates both DAC
outputs.
b
); then, a single command (1000
b
is reserved for the special Sleep
b
(the DAC input code D9-D0 is
b
is used to load DAC A
b
) can be used both
b
LTC1662
loads DAC B,
IN
b
input
7
and