LTC1661 Linear Technology, LTC1661 Datasheet - Page 7

• Manufacturer Part Number: LTC1661
• Description: Micropower Dual 10-Bit DAC in MSOP
• Manufacturer: Linear Technology

OPERATIO
Transfer Function
The transfer function for the LTC1661 is:
where k is the decimal equivalent of the binary DAC input
code D9-D0 and V
Power-On Reset
The LTC1661 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) must not ever exceed the voltage
at V
taken in the power supply turn-on and turn-off sequences
to assure that this limit is observed. See Absolute Maxi-
mum Ratings.
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Control code, the 10-bit Input code and two don’t-care bits.
Table 1. LTC1661 Input Word
After the Input word is loaded into the register (see Figure 1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide Input code data path is then buffered
by two latch registers.
The first of these, the Input Register, is used for loading new
input codes. The second buffer, the DAC Register, is used
for updating the DAC outputs. Each DAC has its own 10-bit
Input Register and 10-bit DAC Register.
A3 A2 A1
Control Code
V
CC
OUT IDEAL
(Pin 6) by more than 0.3V. Particular care should be
(
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
)
U
REF
1024
k
is the voltage at REF (Pin 6).
Input Word
V
Input Code
REF
D0
X1 X0
Don’t
Care
By selecting the appropriate 4-bit Control code (see Table 2)
it is possible to perform single operations, such as loading
one DAC or changing Power-Down status (Sleep/Wake).
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part up.
The DACs can be loaded separately or together, but the
outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the D
is shifted into the 16-bit Shift Register on the positive edge
of SCK. The 4-bit Control code, A3-A0, is loaded first, then
the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last.
When the full 16-bit Input word has been shifted in, CS/LD
is pulled high, causing the system to respond according to
Table 2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110
instruction (see Table 2). In this mode, the digital parts of
the circuit stay active while the analog sections are dis-
abled; static power consumption is greatly reduced. The
reference input and analog outputs are set in a high
impedance state and all DAC settings are retained in
memory so that when Sleep mode is exited, the outputs of
DACs not updated by the Wake command are restored to
their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110
ignored).
To save instruction cycles, the DACs may be prepared with
new input codes during Sleep (control codes 0001
0010
to wake the part and to update the output values.
b
); then, a single command (1000
b
is reserved for the special Sleep
b
(the DAC input code D9-D0 is
b
) can be used both
LTC1661
IN
b
input
7
and