LTC1472 Linear Technology, LTC1472 Datasheet - Page 8

• Manufacturer Part Number: LTC1472
• Description: Protected PCMCIA VCC and VPP Switching Matrix
• Manufacturer: Linear Technology

OPERATION
LTC1472
V
The LTC1472 ensures that the 3.3V and 5V switches are
never turned on at the same time by employing an XOR
function which locks out the 3.3V switch when the 5V
switch is turned on, and locks out the 5V switch when the
3.3V switch is turned on. This XOR function also makes it
possible for the LTC1472 to work with either active-low or
active-high PCMCIA V
tions Information for further details).
V
The LTC1472 has built-in delays to ensure that the 3.3V
and 5V switch are non-overlapping. Further, the gate
charge pumps include circuity which ramps the NMOS
switches on slowly (400 s typical rise time) but turn off
much more quickly (typically 10 s).
V
When either the 3.3V or 5V switch is enabled, a bias
current generator and high frequency oscillator are turned
on. An on-chip capacitive charge pump generates ap-
proximately 12V of gate drive for the internal low R
NMOS V
fore, an external 12V supply is not required to switch the
V
when both switches are turned off.
V
Both V
typical rise time). Turn off time is much quicker
(typically 10 s).
To ensure that both V
discharged, program the switch to the high impedance
mode at least 100 s before turning off the 5V
supply.
V
Two levels of protection are designed into each of the
power switches in the LTC1472. Both V
protected against accidental short circuits with SafeSlot
fold-back current limit circuits which limit the output
current to typically 1A when the V
8
CC
CC
CC
CC
CC
CC
XOR Input Circuitry
Break-Before-Make Switch Control
Bias, Oscillator and Gate Charge Pump
Gate Charge and Discharge Control
Switch Protection
output. The 5V
CC
CC
switches are designed to ramp on slowly (400 s
switches from the 5V
U
IN
CC
supply current drops below 1 A
CC
switch control logic (see Applica-
NMOS switch gates are fully
CC(OUT)
IN
power supply. There-
output is shorted
CC
switches are
IN
DS(ON)
power
THE VPP SWITCHING SECTION
The VPP switching section of the LTC1472 consists of the
following functional blocks:
VPP Switch Input TTL-CMOS Converters
The VPP inputs are designed to accommodate a wide
range of 3V and 5V logic families. The input threshold
voltage is 1.4V with
enable the bias generator, the gate charge pumps and the
protection circuitry. When the inputs are turned off, the
entire circuit is powered down and the V
supply currents drop below 1 A.
VPP Break-Before-Make Switch Control
The VPP input section has built-in delays to ensure that the
VPP switchs are non-overlapping. Further, the gate charge
pumps include circuitry which ramps the NMOS switches
on slowly but turns them off quickly.
VPP Bias, Oscillator and Gate Charge Pump
When either the VPP
is enabled, a bias current generator and high frequency
oscillator are turned on. An on-chip capacitive charge
pump generates approximately 23V of gate drive for the
internal low R
the VPP
NMOS switch is either powered by the external 12V
regulator (if left on) or automatically from a built-in charge
pump powered from the V
supply drops below 10V. The V
below 1 A when switched to either the 0V or Hi-Z mode.
to ground. Both switches also have independent thermal
shutdown which limits the power dissipation to safe
levels.
IN
power supply. The gate of the V
DS(ON)
V
CC
V
0
1
0
1
EN0
CC
IN
NMOS VPP
Switch Truth Table
-VPP
100mV of hysteresis. The inputs
DD
V
CC
OUT
0
0
1
1
supply when the external 12V
EN1
or V
DD
IN
V
-VPP
supply current drops
CC(IN)
CC(OUT)
3.3V
OFF
OFF
5V
OUT
-VPP
DD
CC(IN)
switch from
and VPP
OUT
-VPP
switch
OUT
IN