LTC1416 Linear Technology, LTC1416 Datasheet - Page 7

• Manufacturer Part Number: LTC1416
• Description: Low Power 14-Bit/ 400ksps Sampling ADC
• Manufacturer: Linear Technology

TEST CIRCUITS
APPLICATIONS
CONVERSION DETAILS
The LTC1416 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
A
A
IN
IN
+
–
DBN
(A) Hi-Z TO V
SAMPLE
SAMPLE
V
DAC
+
V
DAC
1k
Figure 1. Simplified Block Diagram
–
OH
Load Circuits for Access Timing
HOLD
HOLD
AND V
U
OL
C
C
TO V
SAMPLE
SAMPLE
C
C
DAC
DAC
C
L
INFORMATION
OH
+
–
U
+
–
SAR
DBN
(B) Hi-Z TO V
ZEROING SWITCHES
+
–
W
COMP
14
HOLD
HOLD
OUTPUT
OL
LATCH
5V
AND V
1k
C
U
L
OH
1416 TC01
TO V
•
•
•
1416 F01
OL
D13
D0
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the A
connected to the sample-and-hold capacitors (C
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 400ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the C
transferring the differential analog input charge onto the
summing junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the A
charges. The SAR contents (a 14-bit data word) which
represents the difference of A
the 14-bit output latches.
DBN
(A) V
1k
Load Circuits for Output Float Delay
OH
TO Hi-Z
100pF
SAMPLE
IN
+
and A
IN
DBN
capacitors to ground,
+
and A
IN
IN
(B) V
+
–
LTC1416
are loaded into
and A
IN
OL
5V
–
TO Hi-Z
1k
inputs are
100pF
IN
SAMPLE
–
1416 TC02
input
7
)