LTC1266 Linear Technology, LTC1266 Datasheet - Page 16

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LTC1266

Manufacturer Part Number
LTC1266
Description
Synchronous Regulator Controller for N- or P-Channel MOSFETs
Manufacturer
Linear Technology
Datasheet

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APPLICATIO S I FOR ATIO
LTC1266
LTC1266-3.3/LTC1266-5
Troubleshooting Hints
Since efficiency is critical to LTC1266 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor, Pin 6.
In continuous mode (I
pin should be a sawtooth with a 0.9V
voltage should never dip below 2V as shown in Figure 9a.
When load currents are low (I
operation should occur with the C
cally falling to ground for periods of time as shown in
Figure 9b.
16
(a) Continuous Mode Operation
(b) Burst Mode Operation
Figure 9. C
C T
U U
LOAD
470
> I
T
3300pF
Waveforms
BURST
LOAD
Figure 10. LTC1266 Layout Diagram (See Layout Checklist)
T
1
2
3
4
5
6
7
8
pin waveform periodi-
C
< I
) the voltage on the C
B
W
TDRIVE
PWR V
PINV
BINH
V
C
I
SENSE
TH
IN
T
BURST
+
C
IN
LTC1266
P-P
IN
) Burst Mode
swing. This
SENSE
BDRIVE
LB
1000pF
PGND
SGND
SHDN
LB
OUT
V
U
FB
IN
+
16
15
14
13
12
11
10
9
LTC1266 • F09
3.3V
0V
3.3V
0V
SHUTDOWN
T
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
If Pin 6 is observed falling to ground at high output
currents, it indicates poor decoupling or improper ground-
ing. Refer to the Board Layout Checklist.
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1266 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 10. Check the follow-
ing in your layout:
1. Are the signal and power grounds segregated? The
2. Does the LTC1266 Sense
LTC1266 signal ground (Pin 12) must return to the
(–) plate of C
source of the bottom-side MOSFET, anode of the
Schottky diode and (–) plate of C
have as short lead lengths as possible.
close to R
able applications, the resistive divider R1 and R2 must
be connected between the (+) plate of C
ground.
L
BOLD LINES INDICATE
HIGH CURRENT PATHS
R1
R2
SENSE
OUT
+
and the (+) plate of C
. The power ground returns to the
C
OUT
R
LTC1266 • F10
SENSE
(Pin 8) connect to a point
V
V
+
+
IN
OUT
IN
, which should
OUT
OUT
? In adjust-
and signal

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