LT1950 Linear Technology, LT1950 Datasheet - Page 9

• Manufacturer Part Number: LT1950
• Description: Single Switch PWM Controller
• Manufacturer: Linear Technology

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OPERATIO
increases the range of MOSFETs that can be selected and
allows applications requiring high gate drive with a large
swing in V
output driver is enabled. The GATE switches between 0V
and V
R
switcher at the BOOST pin is disabled to save power and
only re-enabled when V
boost switcher runs in burst mode operation, asynchro-
nous to the main oscillator. If low V
GATE drive is not required, the BOOST pin is left open and
the V
minimum operational V
8V (required at V
GATE turn on, a PWM latch is set at the start of each main
oscillator cycle. For GATE turn off, the PWM latch is reset
when either the current sense comparator is tripped, the
maximum duty cycle is reached, or the BLANK override
threshold is exceeded.
A resistor divider from the application’s output voltage
generates a voltage at the FB pin that is compared to the
internal 1.23V reference by the error amplifier. The error
amplifier output (COMP) defines the input threshold
(I
voltage is clamped to 100mV. By connecting I
sense resistor in series with the source of the external
MOSFET, the peak switch current is controlled by COMP.
An increase in output load current causing the output
voltage to fall, will cause COMP to rise, increasing I
threshold, increasing the current delivered to the output.
This current mode technique means that the error ampli-
fier commands current to be delivered to the output rather
than voltage. This makes frequency compensation easier
and provides faster loop response to output load tran-
sients.
The current mode architecture requires slope compensa-
tion to be added to the current sensing loop to prevent
subharmonic oscillations which can occur for duty cycles
above 50%. Unlike most current mode converters which
have a slope compensation ramp that is fixed internally,
placing a constraint on inductor value and operating
frequency, the LT1950 has externally adjustable slope
OSC
SENSE
IN2
IN2
pin to ground. When V
) of the current sense comparator. Maximum I
pin shorted to V
at a constant frequency set by a resistor from the
IN
voltage. When V
IN2
U
to enable the GATE output driver). For
IN
IN2
IN
voltage will increase from 3V to
. With V
drops below 10V. The internal
IN2
IN2
reaches 11V, the internal
exceeds 8V, the GATE
IN2
IN
operation with high
shorted to V
SENSE
IN
SENSE
SENSE
to a
the
compensation. A default level of slope compensation is
achieved with the SLOPE pin open. Increased slope com-
pensation can be programmed by reducing the value of
resistance inserted between the SLOPE pin and V
A SYNC pin allows the LT1950 main oscillator to be
synchronized to an external clock . To avoid loss of slope
compensation during synchronization, the free running
main oscillator frequency should be programmed to ap-
proximately 80% of the external clock frequency.
The LT1950 can be placed into shutdown mode when the
SHDN pin drops below an accurate 1.32V threshold. This
threshold can be used to program undervoltage lockout
(UVLO) at V
supplies. SHDN pin current hysteresis also exists to allow
external programming of UVLO voltage hysteresis. When
V
and 6.8V, the V
is a 2.5V reference supplying the majority of LT1950
control circuitry and capable of sourcing up to 2.5mA for
external use.
To prevent noise in the system causing premature turn off
of the external MOSFET the LT1950 has leading edge
blanking. This means the current sense comparator out-
put is ignored during MOSFET turn on and for an extended
period after turn on. The extended blanking period is
adjusted by inserting a resistor from the BLANK pin to
ground. A short to ground defines a minimum default
blanking period. Increased resistance from the BLANK pin
to ground will increase blanking duration. Fault conditions
causing I
and reduce the I
For applications requiring maximum duty cycle clamping,
the V
the pin. The V
in forward converter applications.
Maximum duty cycle follows (105/V
ages between 1.4V to 2.8V. If unused, the V
be shorted to ground, leaving the natural maximum duty
cycle of the part to be typically 95% for 200kHz operation.
IN
and V
SEC
IN2
pin reduces duty cycle for increased voltage on
SENSE
IN
exceed internally set UVLO thresholds of 2.6V
SEC
for current limited or high source resistance
REF
to exceed 125mV will override blanking
SENSE
pin provides a volt-second clamp critical
output becomes active. The V
to GATE delay to 60ns.
SEC
)% for V
SEC
LT1950
pin should
REF
sn1950 1950fs
SEC
REF
output
volt-
9
pin.