LT1765-2.5 Linear Technology, LT1765-2.5 Datasheet - Page 14
![no-image](/images/manufacturer_photos/0/3/388/linear_technology_sml.jpg)
LT1765-2.5
Manufacturer Part Number
LT1765-2.5
Description
Monolithic 3A/ 1.25MHz Step-Down Switching Regulator
Manufacturer
Linear Technology
Datasheet
1.LT1765-2.5.pdf
(20 pages)
APPLICATIO S I FOR ATIO
Figure 8 shows the overall loop response with a 330pF V
capacitor and a typical 100 F tantalum output capacitor.
The response is set by the following terms:
Error amplifier:
DC gain set by g
Pole set by C
Unity-gain set by C
410kHz.
Power stage:
DC gain set by g
Pole set by C
Unity-gain set by C
Tantalum output capacitor:
Zero set by C
The zero produced by the ESR of the tantalum output
capacitor is very useful in maintaining stability. Ceramic
output capacitors do not have a zero due to very low ESR,
but are dominated by their ESL. They form a notch in the
1MHz to 10MHz range. Without this zero, the V
be made dominant. A typical value of 2.2nF will achieve
this.
If better transient response is required, a zero can be
added to the loop using a resistor (R
compensation capacitor. As the value of R
transient response will generally improve, but two effects
limit its value. First, the combination of output capacitor
ESR and a large R
altogether. Second, if the loop gain is not rolled suffi-
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
14
–20
–40
80
60
40
20
0
OUT
10
OUT
F
Figure 8. Overall Loop Response
and R
and C
m
and R
OUT
100
U
F
m
and R
and g
C
L
and g
ESR
FREQUENCY (Hz)
and R
= (2 • 500k • 330p)
may stop loop gain rolling off
L
1k
U
= (2 • 100 • 10)
= (2 • 100 • 0.1)
L
m
m
(assume 5 ) = 5 • 5 = 25.
= (2 • 330p • 850
= (2 • 100 • 5
V
C
C
R
I
L
LOAD
10k
OUT
OUT
C
C
/C
= 330pF
= 850 • 500k = 425.
F
= 5V
= 100 F, 0.1
= 1A
= 0
W
100k
C
) in series with the
PHASE
GAIN
1765 F08
1M
C
–1
is increased,
180
150
120
90
60
30
0
–1
–1
–1
C
)
= 15.9kHz.
U
pole must
–1
= 965Hz.
= 159Hz.
= 8kHz.
–1
)
–1
=
C
ciently at the switching frequency, output ripple will
perturb the V
switching similar to subharmonic oscillation. This may
not be apparent at the output. Small signal analysis will
not show this since a continuous time system is assumed.
If needed, an additional capacitor (C
V
frequency (If R
When checking loop stability, the circuit should be oper-
ated over the application’s full voltage, current and tem-
perature range. Any transient loads should be applied and
the output voltage monitored for a well-damped behavior.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for ex-
ample, a battery powered device with a wall adapter input,
the output of the LT1765 can be held up by the backup
supply with its input disconnected. In this condition, the
SW pin will source current into the V
is held at ground, only the shutdown current of 6 A will be
pulled via the SW pin from the second supply. With the
SHDN pin floating, the LT1765 will consume its quiescent
operating current of 1mA. The V
current to any other components connected to the input
line. If this load is greater than 10mA or the input could be
shorted to ground, a series Schottky diode must be added,
as shown in Figure 9. With these safeguards, the output
can be held at voltages up to the V
rating.
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 10 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, C
the output starts to rise, Q1 turns on, regulating switch
current via the V
output. Output rise time is controlled by the current
through C
is in regulation, Q1 turns off and the circuit operates
normally. R3 is transient protection for the base of Q1.
C
pin to form a pole at typically one fifth the switching
SS
defined by R4 and Q1’s V
C
C
pin enough to cause unstable duty cycle
C
= ~ 5k, C
pin to maintain a constant dv/dt at the
F
= ~ 100pF)
IN
IN
IN
F
) can be added to the
pin will also source
absolute maximum
pin. If the SHDN pin
BE
. Once the output
SS
and Q1. As
sn1765 1765fas