LT1611 Linear Technology, LT1611 Datasheet - Page 8

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LT1611

Manufacturer Part Number
LT1611
Description
Constant-Current/ Constant-Voltage 1.4MHz Step-Up DC/DC Converter
Manufacturer
Linear Technology
Datasheet

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OPERATIO
LT1611
In Figure 11 (also shown on the first page), output capaci-
tor C3 is replaced by a ceramic unit. These large value
ceramic capacitors have ESR of about 2m and result in
very low output ripple. At the 20mV/division scale, output
voltage ripple cannot be seen. Figure 12 pictures the
output and switch nodes at 200ns per division. The output
voltage ripple is approximately 1mV
layout is mandatory to achieve this level of performance.
LOAD CURRENT
8
Figure 11. Replacing C3 with 22 F Ceramic Capacitor
(Taiyo Yuden JMK325BJ226MM) Improves Output
Noise. C
AC COUPLED
20mV/DIV
150mA
50mA
V
OUT
PL
= 1200pF Results in Best Phase Margin
U
Figure 13. Suggested Component Placement. Note Cut in Ground Copper at D1’s Cathode
–V
OUT
100 s/DIV
P–P
GND
+
. Again, good
C3
D1
C2
L1B
1611 F11
R2
L1A
1
2
3
Layout
The LT1611 switches current at high speed, mandating
careful attention to layout for best performance. You will
not get advertised performance with careless layout. Figure 13
shows recommended component placement. Follow this
closely in your printed circuit layout. The cut ground
copper at D1’s cathode is essential to obtain the low noise
achieved in Figures 11 and 12’s oscillographs. Input
bypass capacitor C1 should be placed close to the LT1611
as shown. The load should connect directly to output
capacitor C2 for best load regulation. You can tie the local
ground into the system ground plane at C3’s ground
terminal.
R1
SWITCH VOLTAGE
C1
AC COUPLED
5
4
+
5mV/DIV
5V/DIV
Figure 12. 22 F Ceramic Capacitor at
Output Reduces Ripple to 1mV
Layout Is Essential to Achieve Low Noise
V
OUT
LOAD = 150mA
SHUTDOWN
V
IN
1611 F13
200ns/DIV
P–P
. Proper
1611 F12

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