LT1431C Linear Technology, LT1431C Datasheet - Page 5

• Manufacturer Part Number: LT1431C
• Description: Programmable Reference
• Manufacturer: Linear Technology

PI FU CTIO S
COLL (Pin 1): Open collector of the output transistor. The
maximum pin voltage is 26V. The saturation voltage at
100mA is approximately 1V.
COMP (Pin 2): Base of the driver for the output transistor.
This pin allows additional compensation for complex
feedback systems and shutdown of the regulator. It must
be left open if unused.
V
maximum input voltage is 36V and the minimum to
operate is equal to V
typically 0.6mA.
R
that guarantees 1% accuracy of operation as a 5V shunt
regulator with no external trim. The pin is tied to COLL for
self-contained 5V operation. It may be left open if unused.
See note on parasitic diodes below.
GND-S (Pin 5): Ground reference for the on-chip resistive
divider and shunt regulator circuitry except for the output
transistor. This pin allows external current limit of the
output transistor with one resistor between GND-F (force)
and GND-S (sense).
GND-F (Pin 6): Emitter of the output transistor and sub-
strate connection for the die.
BLOCK
TOP
+
U
(Pin 3): Bias voltage for the entire shunt regulator. The
(Pin 4): Top of the on-chip 5k-5k resistive divider
U
I D AGRA
REF
U
(2.5V). The quiescent current is
W
R
REF
MID
8
7
R
TOP
4
5k
5k
GND-SENSE
5
2.5V
+
–
4mA/V
gm =
V
+
3
R
between R
contained 5V operation. It may be left open if unused.
REF (Pin 8): Control pin of the shunt regulator with a 2.5V
threshold. If V
reduces I
COMP, R
tion circuits that must not be activated on a continuous
basis. Therefore, the absolute maximum DC voltage on
these pins is 6V, well beyond the normal operating condi-
tions.
As with all bipolar ICs, the LT1431 contains parasitic
diodes which must not be forward biased or else anoma-
lous behavior will result. Pin conditions to be avoided are
R
voltage (except for GND-S).
The following pin definitions apply to the Z package.
CATHODE (Pin 1): Corresponds to COLL and V
together.
ANODE (Pin 2): Corresponds to GND-S and GND-F tied
together.
REF (Pin 3): Corresponds to REF.
MID
TOP
(Pin 7): Middle of the on-chip resistive divider string
below R
COMP
2
TOP
B
TOP
to 0.2 A typical.
, R
MID
and GND-S. The pin is tied to REF for self-
MID
+
COLLECTOR
GND-FORCE
> 3V, input bias current cancellation
in voltage and any pin below GND-F in
, and REF have static discharge protec-
1
6
LT1431 • BD01
LT1431
+
5
tied