LT1186 Linear Technology, LT1186 Datasheet - Page 12

• Manufacturer Part Number: LT1186
• Description: DAC Programmable CCFL Switching Regulator(Bits-to-NitsTM)
• Manufacturer: Linear Technology

APPLICATIONS
LT1186F
circuitry provides a ratio of switch current to driver current
of about 50:1.
8-Bit Current Output DAC
The 8-bit current output DAC is guaranteed monotonic and
is digitally adjustable by the 8-bit counter in 256 equal
steps. On power up, the counter resets to 80H and the DAC
assumes its mid-range value. The current output I
drives the I
current programming block. The DAC has its own 1.24V
bandgap reference and a voltage to current converter that
is trimmed at wafer sort to provide the precision full-scale
current reference. Over temperature, the current output of
the DAC is 50 A 6%.
Digital Interface
On power-up, a logic high at CS configures the DAC into
pulse mode. If CS is ever pulled low, the chip configures
into SPI mode until V
mode, a logic high at D
only mode. If UP/DN (D
configures into increment/decrement mode until V
sets. These modes are illustrated in Figure 1.
12
Figure 1a. Tree Diagram (LT1186F DAC Operating Modes)
POWER ON
GOES LOW
SPI MODE
CS EVER
CCFL
pin and sets control current for the lamp
Figure 1b. SPI Mode Setup
D
SINGLE DAC
EVER GOES
INCREMENT/
DECREMENT
IN
U
(UP/DN)
IN
CC
LOW
IN
puts the counter into increment-
INFORMATION
) is ever pulled low, the counter
U
resets. On power-up in pulse
PULSE MODE
CS STAYS
HIGH
CS EVER GOES LOW
W
INCREMENT-
D
HIGH
IN
ONLY
LT1186F • F01a
STAYS
LT1186F • F01b
CS
V
CC
U
CC
OUT
re-
Standard SPI Mode
Refer to the serial interface operating sequence in Figure
2. A falling edge at CS initiates the data transfer. After the
falling CS is recognized, D
The clock (CLK) synchronizes the data transfer. Each input
bit shifts into D
edge and each previous data bit shifts out of D
ning with the MSB on the falling CLK edge. After the 8-bit
serial input data is shifted in, a rising edge at CS transfers
the data into the counter, the DAC assumes the new value
I
returns to a high impedance state.
1-Wire Interface (Pulse Mode)
In increment-only pulse mode, each rising edge of CLK
increments the upper six bits of the counter by one count.
When incremented beyond 11111100B, the counter rolls
over and sets the DAC to the minimum value 00000000B.
Therefore, a single pulse applied to CLK increases the
upper 6-bit counter by one-step, and 63 pulse applied to
CLK decreases the counter by one-step. The last two LSBs
are always zero in this mode. I
(50 A)/255. The upper 6-bit counter = B
B
mode, tie CS and D
OUT
1
= B
POWER ON
POWER ON
= (8-bit serial input data)(50 A)/255 and the D
Figure 1d. Pulse Mode Setup (Increment/Decrement)
0
= 0. To configure the LT1186F into increment-only
Figure 1c. Pulse Mode Setup (Increment Only)
IN
beginning with the MSB on the rising CLK
IN
to V
CC
OUT
.
OUT
UP/DN EVER GOES LOW
comes out of three-state.
= (B
7
B
7
6
B
B
6
5
B
B
5
CS ALWAYS HIGH
D
CS ALWAYS HIGH
4
V
V
UP/DN
B
IN
CC
CC
B
OUT
4
ALWAYS HIGH
3
B
B
3
OUT
LT1186F • F01d
2
B
begin-
LT1186F • F01c
B
2
1
and
B
pin
0
)