IR3841WMPBF International Rectifier, IR3841WMPBF Datasheet - Page 15

• Manufacturer Part Number: IR3841WMPBF
• Description: HIGHLY EFFICIENT INTEGRATED 8A SYNCHRONOUS BUCK REGULATOR
• Manufacturer: International Rectifier

Thermal Shutdown
Temperature
IR3841W. The trip threshold is typically set to
140
shutdown
discharges the soft start capacitor.
Automatic restart is initiated when the sensed
temperature drops within the operating range.
There is a 20
shutdown threshold.
Output Voltage Sequencing
The
programmable sequencing options using Seq,
Enable and Power Good pins.
Fig. 8a. Simultaneous Power-up of the slave
Rev 5.0
Through these pins, voltage sequencing such as
simultaneous
implemented. Figure 8. shows simultaneous
sequencing
power-up, the voltage at the Seq pin of the slave
reaches 0.7V before the Fb pin of the master. For
R
the slave follows that of the master until the
voltage at the Seq pin of the slave reaches 0.7 V.
After the voltage at the Seq pin of the slave
exceeds 0.85V, the internal 0.7V reference of
the slave dictates its output voltage.
o
E
C. When trip threshold is exceeded, thermal
/R
F
IR3841W
with respect to the master.
=R
turns
C
/R
Simultaneous Powerup
D
sensing
configurations.
o
, therefore, the output voltage of
C hysteresis in the thermal
and
off
can
both
is
accommodate
sequential
Vo1
Vo2
provided
MOSFETs
In
simultaneous
can
inside
user
and
be
RE
RF
Vo(master)
1.5V <Vin<16V
4.5V <Vcc<5.5V
Fig. 8b. Application Circuit for Simultaneous
Power Good Output
The IC continually monitors the output voltage via
Feedback (Fb pin). The feedback voltage forms
an input to a window comparator whose upper
and lower thresholds are 0.805V and 0.595V
respectively. Hence, the Power Good signal is
flagged when the Fb pin voltage is within the
PGood window, i. e. between 0.595V to 0.805V,
as shown in Fig .9. The PGood pin is open drain
and it needs to be externally pulled high. High
state indicates that output is in regulation. Fig. 9a
shows the PGood timing diagram for non-
tracking operation. In this case, during startup,
PGood goes high after the SS voltage reaches
2.1V if the Fb voltage is within the PGood
comparator window. Fig. 9a. and Fig 9.b. also
show a 256 cycle delay between the Fb voltage
entering within the thresholds defined by the
PGood window and PGood going high.
PGood
Sequencing
Seq
Vcc
Rt
SS/ SD
PGood
Enable
Gnd
IR3841WMPbF
Vin
PGnd
OCSet
Comp
Boot
SW
Fb
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RC
RD
15
Vo(slave)