AD5235 Analog Devices, AD5235 Datasheet - Page 3

• Manufacturer Part Number: AD5235
• Description: 8-Bit Dual Nonvolatile Memory Digital Potentiometer
• Manufacturer: Analog Devices

Nonvolatile Memory Digital Potentiometers
ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS
= +V
Parameter
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 8)
Clock Cycle Time
Input Clock Pulse Width
CS Setup Time
Data Setup Time
Data Hold Time
CLK Shutdown Time
CS Rise to Clock Rise Setup
CS High Pulse Width
CLK to SDO Propagation Delay
Store to Nonvolatile EEMEM Save Time
CS to SDO - SPI line acquire
CS to SDO - SPI line release
RDY Rise to CLK Rise
Startup Time
CLK Setup Time
Preset Pulse Width
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Timing Diagram
REV PrD 6 NOV, 2000
Information contained in this Product Concept data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara,
CA. TEL[phone]; FAX [phone]; [e-mail]
DD
Typicals represent average readings at +25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step
change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. I
INL and DNL are measured at V
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.
Resistor terminals A,B,W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
P
All dynamic characteristics use V
See timing diagram for location of measured values. All input control voltages are specified with t
measured using both V
Propagation delay depends on value of V
Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms.
DISS
, V
is calculated from (I
B
= 0V, -40°C < T
DD
DD
= +3V or +5V.
x V
DD
A
W
DD
=+5V).
< +85°C unless otherwise noted.)
9
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
= +5V.
PRELIMINARY TECHNICAL DATA
DD
, R
10
S D O
S D O
R D Y
PULL_UP
C L K
Symbol
S D I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C S
PR
4
6
7
8
9
10
11
12
13
14
15
16
1
2
5
1
2
, t
DD
, and C
3
= +5V.
L
see applications text.
t
12
t
16
Conditions
Clock level high or low
From Positive CLK transition
From Positive CLK transition
R
Applies to Command 2
For 1 CLK period (t
t
14
L
t
4
= 1K , C
SDO
t
5
M S B
M S B
M S B
1
Figure 1. Timing Diagram
CLK IDLES LOW
L
t
< 20pF
10
t
3
4
1
- t
3
H
, 3
R
= 1 CLK period)
=t
F
H
=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are
SDO
2
CLK IDLES HIGH
W
t
= V
3
L S B
L S B
DD
/R for both V
t
t
2
6
L S B
A
t
7
= V
Min
DD
20
10
10
10
10
50
(V
DD
5
5
0
1
=+3V or V
t
t
DD
and V
t
13
15
8
t
= +3V±10% to +5V±10% and V
9
B
t
= 0V.
11
DD
Typ
=+5V.
1
Max
25
25
AD5235
Units
ms
ms
SS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
=0V, V
A