AD5170 Analog Devices, AD5170 Datasheet - Page 20

• Manufacturer Part Number: AD5170
• Description: 256-Position Two-Time Programmable I2C Digital Potentiometer
• Manufacturer: Analog Devices

AD5170
I
The 2-wire I
1.
2.
2
C COMPATIBLE 2-WIRE SERIAL BUS
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 45). The
following byte is the slave address byte, which consists of
the slave address followed by an R/ W bit (this bit deter-
mines whether data is read from or written to the slave
device). AD0 and AD1 are configurable address bits which
allow up to four devices on one bus (see Table 7).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/ W bit is high, the master will read
from the slave device. If the R/ W bit is low, the master will
write to the slave device.
In the write mode, the second byte is the instruction byte.
The first bit (MSB), 2T, of the instruction byte is the second
trim enable bit. A logic low selects the first array of fuses
and a logic high selects the second array. This means that
after blowing the fuses with trim#1, the user still has
another chance to blow them again with trim#2. Note that
using trim#2 before trim#1 effectively disables trim#1 and
in turn only allows one-time programming.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to note
that the shutdown operation does not disturb the contents
of the register. When brought out of shutdown, the
previous setting is applied to the RDAC. Also, during
shutdown, new settings can be programmed. When the
part is returned from shutdown, the corresponding VR
setting is applied to the RDAC.
The third MSB, T, is the OTP (one-time programmable)
programming bit. A logic high blows the poly fuses and
programs the resistor setting permanently. For example, if
the user wanted to blow the first array of fuses, the
instruction byte would be 00100XXX. If the user wanted to
blow the second array of fuses, the instruction byte would
be 10100XXX. A logic low of the T bit simply allows the
device to act as a typical volatile digital potentiometer.
The fourth MSB must always be at Logic 0.
2
C serial bus protocol operates as follows:
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3.
4.
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC has
acknowledged its slave address and instruction bytes in the
write mode, the RDAC output updates on each successive byte.
If different instructions are needed, the write/read mode has to
start again with a new slave address, instruction, and data byte.
Similarly, a repeated read function of the RDAC is also allowed.
The fifth MSB, OW, is an overwrite bit. When raised to a
logic high, OW allows the RDAC setting to be changed
even after the internal fuses have been blown. However
once OW is returned to a logic zero, the position of the
RDAC returns to the setting prior to overwrite. Because
OW is not static, if the device is powered off and on, the
RDAC presets to midscale or to the setting at which the
fuses were blown, depending on whether or not the fuses
have been permanently set already.
The remainder of the bits in the instruction byte are don’t
cares (see Figure 45).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see
Figure 44).
In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference from the write mode, with eight
data bits followed by an acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 46).
Following the data byte, the validation byte contains two
validation bits, E0 and E1. These bits signify the status of
the one-time programming (see Figure 46).
After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10
condition (see Figure 45). In read mode, the master issues a
No Acknowledge for the 9
remains high). The master then brings the SDA line low
before the 10
STOP condition (see Figure 46).
th
clock pulse, which goes high to establish a
th
clock pulse to establish a STOP
th
clock pulse (i.e., the SDA line