MCM63F733A Motorola, MCM63F733A Datasheet - Page 14

• Manufacturer Part Number: MCM63F733A
• Description: 128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
• Manufacturer: Motorola

MCM63F733A
14
SLEEP MODE
on the MCM63F733A. It allows the system designer to place
the RAM in the lowest possible power condition by asserting
ZZ. The sleep mode timing diagram shows the different
modes of operation: Normal Operation, No READ/WRITE
Allowed, and Sleep Mode. Each mode has its own set of
constraints and conditions that are allowed.
times prior to sleep and t ZZREC nanoseconds after re-
covering from sleep. Clock (K) must also meet cycle, high,
and low times during these periods. Two cycles prior to sleep,
initiation of either a read or write operation is not allowed.
sleep and during recovery from sleep, the assertion of either
ADSC, ADSP, or any write signal is not allowed. If a write
operation occurs during these periods, the memory array
may be corrupted. Validity of data out from the RAM can not
be guaranteed immediately after ZZ is asserted (prior to
being in sleep).
RAM disconnects its internal clock buffer. The external clock
A sleep mode feature, the ZZ pin, has been implemented
Normal Operation: All inputs must meet setup and hold
No READ/WRITE: During the period of time just prior to
Sleep Mode: The RAM automatically deselects itself. The
ADDR
SE3
DQ
W
G
K
Motorola Memory Prefix
Part Number
A
Q(A)
Figure 5. Example Configuration as Non–Burst Synchronous SRAM
B
Full Part Numbers — MCM63F733ATQ10
Q(B)
READS
C
APPLICATION INFORMATION
MCM
ORDERING INFORMATION
Q(C)
(Order by Full Part Number)
D
MCM63F733ATQ10R
63F733A XX
Q(D)
may continue to run without impacting the RAMs sleep cur-
rent (I ZZ ). All inputs are allowed to toggle — the RAM will not
be selected and perform any reads or writes. However, if
inputs toggle, the I ZZ (max) specification will not be met.
NON–BURST SYNCHRONOUS OPERATION
— and other high end MPU–based systems, these SRAMs
can be used in other high speed L2 cache or memory
applications that do not require the burst address feature.
Most L2 caches designed with a synchronous interface can
make use of the MCM63F733A. The burst counter feature of
the BurstRAM can be disabled, and the SRAM can be con-
figured to act upon a continuous stream of addresses. See
Figure 5.
NOTE: Although X is specified in the table as a don’t care, the pin
CONTROL PIN TIE VALUES EXAMPLE
Sync Non–Burst,
Pipelined SRAM
Although this BurstRAM has been designed for PowerPC
Non–Burst
X
must be tied either high or low.
MCM63F733ATQ11
MCM63F733ATQ11R
X
D(E)
E
Blank = Trays, R = Tape and Reel
Speed (10 = 10 ns, 11 = 11 ns)
Package (TQ = TQFP)
ADSP
H
D(F)
F
ADSC
L
WRITES
MOTOROLA FAST SRAM
ADV
D(G)
H
G
SE1
(H
L
V IH , L
D(H)
H
SE2
H
V IL )
LBO
X