U425 Micross, U425 Datasheet
U425
Manufacturer Part Number
U425
Description
Low Leakage
Manufacturer
Micross
Datasheet
1.U425.pdf
(1 pages)
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Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
The U425 monolithic dual n-channel JFET is designed
to provide very high input impedance for differential
amplification and impedance matching. Among its
many unique features, this series offers operating gate
current specified at -500 fA. The U425 is a direct
replacement for discontinued Siliconix U425.
The hermetically sealed TO-71 & TO-78 packages are
well suited for military applications. The 8 Pin P-DIP
and 8 Pin SOIC provide ease of manufacturing, and the
symmetrical pinout prevents improper orientation.
(See Packaging Information).
U425 Applications:
Available Packages:
U425 in TO-71 & TO-78
U425 in PDIP & SOIC
U425 available as bare die
Please contact
Email:
SYMBOL
‐I
I
‐I
GSS
I
BV
V
GSS
BV
G
CMR
G
Y
C
Y
I
GS(off)
V
max.
C
Y
NF
Y
max.
e
DSS
max.
OSS
RSS
fSS
max.
GGO
GS
OS
ISS
fS
GSS
n
chipcomponents@micross.com
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Ultra Low Input Current Differential Amps
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The U425 is a high input impedance Monolithic Dual N-Channel JFET
Linear Systems replaces discontinued Siliconix U425
COMMON MODE REJECTION
Gate‐To‐Gate Breakdown
OUTPUT CONDUCTANCE
‐20 log | ∆V
‐20 log | ∆V
TRANSCONDUCTANCE
Breakdown Voltage
At Full Conduction
CHARACTERISTICS
High Temperature
High Temperature
Typical Operation
DRAIN CURRENT
Operating Range
Reverse Transfer
for full package and die dimensions
Pinchoff voltage
GATE CURRENT
Full Conduction
Full Conduction
GATE VOLTAGE
Full Conduction
CAPACITANCE
Operating
Operating
Voltage
NOISE
Figure
Input
GS1‐2
GS1‐2
/ ∆V
/ ∆V
DS
DS
|
|
MIN.
300
120
40
40
60
HIGH INPUT IMPEDANCE
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
MONOLITHIC DUAL
N-CHANNEL JFET
FEATURES
HIGH INPUT IMPEDANCE
HIGH GAIN
LOW POWER OPERATION
ABSOLUTE MAXIMUM RATINGS
@ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
Maximum Voltage and Current for Each Transistor – Note 1
‐V
‐V
‐I
Maximum Power Dissipation
Device Dissipation @ Free Air – Total 400mW @ +125°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
|∆V
| V
TYP.
200
0.1
60
90
90
20
10
G(f)
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
GSS
DSO
TO-71 / TO-78 (Top View)
GS1‐2
U425
GS1‐2
| max.
/∆T|max.
MAX.
1500
1000
350
250
2.0
1.8
.25
1.0
1.0
3.0
3.0
1.5
10
70
‐‐
‐‐
‐‐
‐‐
‐‐
1
Gate Voltage to Drain or Source
Drain to Source Voltage
Gate Forward Current
CHARACTERISTICS
OFFSET VOLTAGE
TEMPERATURE
DRIFT VS.
nV/√Hz
UNITS
µmho
µmho
µmho
µmho
µA
pA
pA
pA
nA
dB
dB
dB
pF
pF
V
V
V
V
I
V
V
V
V
I
gfs = 120µmho MIN
V
VALUE UNITS
P-DIP / SOIC (Top View)
T
T
G
A
A
GS(OFF)
= 0.25pA MAX
V
25
15
V
= +125°C
= +125°C
DG
DG
DG
G
DG
V
DS
∆V
∆V
= 1µA I
DS
V
= 10V I
= 10V I
V
= 10V I
= 10V I
= 10V V
V
V
V
= 2V MAX
V
= 10V V
DS
DS
V
DG
DG
DG
DS
DS
DS
DS
DS
= 10 to 20V I
= 5 to 10V I
µV/°C
= 10V I
= 10V I
= 10V I
= 10V I
= 10V V
= 10V V
= 0V V
= 0 I
mV
CONDITIONS
‐65°C to +150°C
+150°C
40V
40V
10mA
D
D
D
f = 10Hz
= 30µA f = 1KHz
= 30µA f = 10Hz
= 30µA R
D
GS
GS
CONDITIONS
V
T
V
= 30µA f = 1kHz
D
= 0 f = 1MHz
= 0V f = 1kHz
A
DG
DG
= 0 I
=‐55°C to +125°C
=10V, I
=10V, I
GS
D
G
D
D
GS
GS
D
= 30µA
D
= 20V
D
=1nA
= 1nA
= 30µA
= 30µA
= 30µA
= 30µA
= 0V
= 0V
G
= 10MΩ
D
D
=30µA
=30µA
S
= 0
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