ZEN2044F Zenic, ZEN2044F Datasheet - Page 8

• Manufacturer Part Number: ZEN2044F
• Description: 33MHz Up/down Counter
• Manufacturer: Zenic

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4-2. Command mode
4-2-1. Mode 0 [after executing command(90H) or system reset]
4-2-2. Mode 1 [after executing command(91H)]
4-3. Selection of counter operation mode
mode you use(Mode 0 or Mode 1). The system mode is fixed by executing the system mode set command
(90H or 91H).
UD/AB , SEL 0, SEL 1 and SEL 2(these signals should be static and not set by the CPU). Refer to
Table 4 for detail.
UD/AB
The
The type of counter pulse and the mode of clearing counter by Z input depend on the condition of
is available.
instruction sets of Mode 1. And two sets of the refrence register and the comparator are available.
EXTB
EXTB
1
0
ZEN2044F
n
n
n
n
SEL 2
is set as a universal input terminal U. One set of the refrence register and the comparator
is set as an output terminal. Both EXTA
n
*
0
0
0
1
1
1
0
1
n
has the following two system modes. First of all, it is necessary to determine which
SEL 1
n
*
0
0
1
0
0
1
1
1
n
SEL 0
n
0
1
0
0
1
0
1
1
*
n
Up/down pulse
Phase-shifted(single)
Phase-shifted(double)
Phase-shifted(quad)
Phase-shifted(single)
Phase-shifted(double)
Phase-shifted(quad)
Single pulse(single)
Single pulse(double)
Pulse input(Edge eval.)
Table 4
- 8 -
n
and EXTB
n
can be controled by the
Asynchronous clear
Synchronous clear
Asynchronous clear
Asynchronous clear
(
Clear mode
Z2044G00 ZENIC INC.
)