74LVC74AD,118 NXP Semiconductors, 74LVC74AD,118 Datasheet
74LVC74AD,118
Specifications of 74LVC74AD,118
74LVC74AD-T
935260734118
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74LVC74AD,118 Summary of contents
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Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 06 — 4 June 2007 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) ...
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... NXP Semiconductors 4. Functional diagram 4 10 1SD 2SD 1CP CP 11 2CP 1RD 2RD 1 13 mna418 Fig 1. Logic symbol Fig 4. Logic diagram for one flip-flop 74LVC74A_6 Product data sheet Dual D-type flip-flop with set and reset; positive-edge trigger mna419 Fig 2. IEC logic symbol ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 1RD 1CP 74 1SD GND 7 001aad106 Fig 5. Pin configuration for SO14 and (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW data input 1CP 3 clock input (LOW-to-HIGH, edge-triggered) ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input nSD nRD [ HIGH voltage level L = LOW voltage level X = don’t care [1] Table 4. Function table Input nSD nRD [ HIGH voltage level L = LOW voltage level = LOW-to-HIGH transition Q = state after the next LOW-to-HIGH CP transition n don’t care 7 ...
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... NXP Semiconductors 8. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage o T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation nCP to nQ, nQ; see pd delay nSD to nQ, nQ; see nRD to nQ, nQ; see pulse width clock HIGH or LOW; see set or reset LOW; see ...
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... NXP Semiconductors [ used to determine the dynamic power dissipation ( input frequency in MHz output frequency in MHz output load capacitance supply voltage in Volts number of inputs switching sum of the outputs 11. AC waveforms nD input nCP input nQ output nQ output The shaded areas indicate when the input is permitted to change for predictable output performance. ...
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... NXP Semiconductors nCP input nSD input nRD input nQ output nQ output < 2 and V are typical output voltage levels that occur with the output load Fig 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths, ...
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... NXP Semiconductors Test data is given in Table 9. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z T Fig 9. Load circuitry for switching times Table 9. Test data Supply voltage 1.2 V 2 3.6 V ...
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... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 11. Package outline SOT337-1 (SSOP14) ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74LVC74A_6 20070604 • Modifications: Change of hold time in ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history ...