TS80C52zzz-MIC Atmel Corporation, TS80C52zzz-MIC Datasheet - Page 17

• Manufacturer Part Number: TS80C52zzz-MIC
• Description: 8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless
• Manufacturer: Atmel Corporation

TS80C52X2 Serial I/O
Port
Framing Error Detection
Figure 6. Framing Error Block Diagram
Figure 7. UART Timings in Mode 1
4184E–8051–09/02
SMOD0=X
SMOD0=1
SM0/FE
SMOD1
RXD
FE
RI
The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-
taneously and at different baud rates
Serial I/O port includes the following enhancements:
•
•
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-
ter (See Figure 6).
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 9.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 7. and Figure 8.).
SMOD0
SM1
Framing error detection
Automatic address recognition
Start
bit
SM2
-
D0
REN
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD = 0)
POF
To UART framing error control
D1
TB8
GF1
D2
RB8
GF0
D3
Data byte
D4
PD
TI
D5
IDL
RI
D6
SCON (98h)
PCON (87h)
D7
Stop
bit
TS8xCx2X2
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