AD9257BCPZRL7-65 Analog Devices, Inc., AD9257BCPZRL7-65 Datasheet
AD9257BCPZRL7-65
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AD9257BCPZRL7-65 Summary of contents
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... ADC D– G LVDS SERIAL ADC D– H LVDS FCO+ 1.0V DATA FCO– RATE SERIAL PORT DCO+ MULTIPLIER INTERFACE DCO– CSB SDIO/ SCLK/ CLK+ CLK– DFS DTP Figure 1. AD9637 (12-Bit Octal ADC). www.analog.com ©2011 Analog Devices, Inc. All rights reserved. ...
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AD9257 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Table of Contents .............................................................................. 2 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC ...
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Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error ...
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AD9257 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR 9.7 MHz IN f ...
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Data Sheet 1 Parameter CROSSTALK Crosstalk (Overrange Condition) 2 ANALOG INPUT BANDWIDTH, FULL POWER 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Overrange ...
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AD9257 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. 1 Parameter , 2 3 CLOCK Input Clock Rate Conversion Rate ...
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Data Sheet Timing Diagrams N – 1 VIN± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO D– – 1 VIN± CLK– CLK+ t CPD DCO– DCO+ ...
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AD9257 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND Digital Outputs (D± x, DCO+, DCO−, FCO+, FCO−) to AGND CLK+, CLK− to AGND VIN+ x, VIN− AGND SCLK/DTP, SDIO/DFS, CSB to AGND SYNC, ...
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Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INDICATOR Table 8. Pin Function Descriptions Pin No. Mnemonic 0, EP AGND, Exposed Pad 11, 12, 37, AVDD 42, 45, 48, 51, 59, 62 13, 36 DNC 14, 35 ...
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AD9257 Pin No. Mnemonic 54 RBIAS 55 SENSE 56 VREF 57 VCM 58 SYNC 60, 61 VIN+ E, VIN− E 63, 64 VIN− F, VIN+ F Description Sets analog current bias. Connect to 10 kΩ (1% tolerance) resistor to ground. ...
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Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD9257-65 0 65MSPS 9.7MHz AT –1dBFS –15 SNR = 74.7dB (75.7dBFS) SFDR = 93.5dBc –30 –45 –60 –75 –90 –105 –120 –135 FREQUENCY (MHz) Figure 6. Single-Tone 16k FFT ...
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AD9257 0 –20 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with MHz and f = ...
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Data Sheet 450,000 400,000 350,000 300,000 250,000 200,000 150,000 100,000 50,000 0 OUTPUT CODE Figure 18. Input-Referred Noise Histogram, f 2.0 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 OUTPUT CODE Figure 19. INL 9.7 MHz, ...
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AD9257 AD9257-40 0 40MSPS –15 9.7MHz AT –1dBFS SNR = 74.8dB (75.8dBFS) SFDR = 96.9dBc –30 –45 –60 –75 –90 –105 –120 –135 FREQUENCY (MHz) Figure 21. Single-Tone 16k FFT with f = 9.7 ...
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Data Sheet 120 SFDRFS 100 SNRFS 80 60 SFDR 40 SNR 20 0 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 27. SNR/SFDR vs. Analog Input Level 105 SFDR 100 SNRFS 75 ...
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AD9257 2.0 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 OUTPUT CODE Figure 33. INL 9.7 MHz SAMPLE –0.2 –0.4 –0.6 –0.8 –1 MSPS Rev Page Data ...
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Data Sheet EQUIVALENT CIRCUITS AVDD VIN± x Figure 35. Equivalent Analog Input Circuit AVDD 5Ω CLK+ 15kΩ AVDD 15kΩ 5Ω CLK– Figure 36. Equivalent Clock Input Circuit AVDD 30kΩ 350Ω SDIO/DFS 30kΩ Figure 37. Equivalent SDIO/DFS Input Circuit DRVDD V ...
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AD9257 THEORY OF OPERATION The AD9257 is a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the ...
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Data Sheet Differential Input Configurations There are several ways to drive the AD9257 passively. However, optimum performance is achieved by driving the analog input differentially. Using a differential double balun configuration to drive the AD9257 provides excellent performance and a ...
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AD9257 If the internal reference of the AD9257 converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 48 shows how the internal reference voltage is affected by loading. 0 –0.5 –1.0 ...
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Data Sheet If a low jitter clock source is not available, another option couple a differential PECL signal to the sample clock input pins, as shown in Figure 52. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 excellent jitter performance. A third ...
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AD9257 Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f ) due only to aperture jitter (t ) can be calculated by A ...
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Data Sheet DIGITAL OUTPUTS AND TIMING The AD9257 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SPI. The ...
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AD9257 Figure 59 shows an example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on standard FR-4 material. 400 EYE: ALL ...
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Data Sheet Two output clocks are provided to assist in capturing data from the AD9257. The DCO is used to clock the output data and is equal to 7× the sample clock (CLK) rate for the default mode of operation. ...
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AD9257 The PN sequence short pattern produces a pseudorandom bit 9 sequence that repeats itself every 2 − 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of ...
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Data Sheet BUILT-IN OUTPUT TEST MODES The AD9257 includes a built-in test feature designed to enable verification of the integrity of each data output channel, as well as to facilitate board level debugging. Various output test options are provided to ...
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AD9257 SERIAL PORT INTERFACE (SPI) The AD9257 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and ...
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Data Sheet HARDWARE INTERFACE The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9257. The SCLK pin and the CSB pin function as inputs when using the SPI ...
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AD9257 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the ...
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Data Sheet MEMORY MAP REGISTER TABLE The AD9257 uses a 3-wire interface and 16-bit addressing and, therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 and Bit 4 are set to 1. When ...
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AD9257 Reg. Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0x0B Clock divide Open Open (global) 0x0C Enhancement Open Open control 0x0D Test mode (local User input test mode except for single sequence resets ...
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Data Sheet Reg. Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0x19 USER_PATT1_LSB B7 B6 (global) 0x1A USER_PATT1_MSB B15 B14 (global) 0x1B B7 B6 USER_PATT2_LSB (global) 0x1C USER_PATT2_MSB B15 B14 (global) 0x21 Serial control LVDS (global) output LSB first ...
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AD9257 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Interfacing to High Speed ADCs via SPI. Device Index (Register 0x04 and Register 0x05) There are certain features in the ...
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Data Sheet Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Table 19. Input Clock Phase Adjust Options Input Clock Phase Number of Input Clock Cycles of Adjust, Bits[6:4] Phase Delay 000 (Default) 0 001 1 010 2 011 ...
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AD9257 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the it is recommended that the designer become familiar with these guidelines, which describes the special circuit connections and layout requirements that are needed for certain pins. POWER AND ...
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... MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9257BCPZ-40 −40°C to +85°C AD9257BCPZRL7-40 −40°C to +85°C AD9257BCPZ-65 −40°C to +85°C AD9257BCPZRL7-65 −40°C to +85°C AD9257-65EBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 TOP VIEW BSC BSC SQ ...
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AD9257 NOTES Rev Page Data Sheet ...
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Data Sheet NOTES Rev Page AD9257 ...
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... AD9257 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10206-0-10/11(0) Rev Page Data Sheet ...