AD900 Analog Devices, Inc., AD900 Datasheet - Page 6

• Manufacturer Part Number: AD900
• Description: Highspeed 6-bit Aidconverter
• Manufacturer: Analog Devices, Inc.

ANALOGDEVICES fAX-ON-DEMAND HOTLINE
The ratio of the rms signal arnplirude to the rms value of
Signal-to-Noise Ratio (SNR)
"noise"
ponents, including harmonics bUt excluding dc, with an analog
input signal IdB below full scale.
Transient Response
The time required for the converter to achieve 6-bit accuracy
when a full scale step function input is applied to the unit.
Two-Tone Intermodulation Distortion (IMD) Rejection
The ratio of the power of a tWo-tone signal to the power of the
strongest third-order IMD signal.
THEORY OF OPERATION
Refer to the block diagram of the AD9016 AID converter.
"Flash" architecture used in the AD9006 and AD9016 units
converter in many applications. The analog input signal is im-
makes it unnecessary to use a track-and-hold (T/H) ahead of the
pressed across 64 parallel comparator stages.
Bias points of these comparators are established by the voltages
applied to the reference ladder via + VREF>MIDSCALEREF and
The outputs of the comparators are applied to the decoding
and can also be used as a "flag" for indicating positive out-of-
Capturing output data at the (guaranteed) encode rates of
470MSPS of the AD9016 is simplified by virrue of using two
logic; from here, the data are applied to oUtput latches as six
bits of digital data and an overflow bit. The overflow bit can be
used to stack converters to obtain additional bits of resolution
range inputs.
Data Ready pulses. OUtput data words alternate between Bank
A and Bank B; this allows clocking demultiplexed data from the
AD9016 at half the converter's sample rate.
The Data Ready pulses track the propagation delay of the out-
put data and relieve the need to build an external clock circuit
range.
user to capture oUtput data with lOOK ECL logic even when the
converter is operating at 470MSPS. The AD9016 introduces
only one pipeline delay in the processing of these digital output
data, thereby reducing the number of clock cycles required to
obtain the digital representation of the analog input at the ap-
The analog input voltage range is determined by the user-
-VREF'
for tracking prop delay over the full operating temperatUre
Demultiplexed ports connected to Bank A and Bank B allow the
propriate output port.
supplied voltage references: + VREFand
can be adjusted between -I V and + IV. In all cases, + VREF
REV. A
Parameter
RECOMMENDED
ANALOG
+Vs
-Vs
+VREF
-V REF
>
which is defined as the sum of all other spectral com-
INPUT
OPERATING CONDITIONS
Min
+4.75
-5.46
-V REF
-l.l
-1.0
Input Voltage
-
Nominal
+ 1.0
-1.0
+5.00
-5.20
Page
-
V
REF' The references
21
Max
+ 1.1
+5.25
-4.94
+ VREF
+1.0
-7-
00
should be greater than
tween the references should not exceed 2.IV. MIDSCALE
V
converter.
Another attractive feature of the analog input characteristics of
flash converters, this value is three or four times larger> making
The AD9OO6is identical to the AD9016 in performance specifi-
cations; it is best suited for systems in which demultiplexing is
not performed immediately after the flash converter. As in the
AD9016, the AD9006 produces Data Ready pulses on chip;
these can be used to clock external latches.
the AD9016 is its low input capacitance of 8pF. In many other
them difficult to drive at high input frequencies.
For those applications in which a single outpUt port is preferred,
the recommended choice is the AD9006 AID converter.
There are two control pins for determining the format of the
output data on the AD9006/AD9016. BIT INVERT (MSB) al-
lows the user to invert the most significant bit (DOs); and Do-
The AD9006/AD9016 Truth Table elsewhere in the data sheet
provides the necessary information to select among binary, in-
verted binary, twos complement and inverted twos complement
coding schemes.
D4 INVERT allows the five least significant bits to be inverted.
The OVERFLOW INHIBIT pin controls the overflow bit
(called out as OVERFLOW BIT in the AD9OO6,and OVER-
FLOW A and OVERFLOWB in the AD9016). In normal opera-
tion, the OVERFLOW INHIBIT is connected to -5.2V, and
OVERFLOW will be a digital HIGH whenever the analog inpUt
voltage exceeds the most positive comparator reference
(+ VSENSE)' T he digital outputs (Do- Ds) will be LOW, i.e.,
This feature means two AD9OO6devices can be cascaded or
Connecting OVERFLOW INHIBIT to ground forces the
overflow bit to remain low and disables the remrn-to-zer9
operation.
"sa INVERT 13
returned-tv-zero operation.
"stacked" to obtain seven-bit operation, as shown in the dia-
gram below.
-
REF
""'NVERT
A~~~
can be used to improve the integral linearityof the
~
2
.
(Dotted Area Not Included in AD9006)
AD9016 Functional Block Diagram
R
-
V
REF; and the differential voltage be-
AD9006/AD9016
AD9016
LATCH"
OUTPUT
..r<. .
,.)
31) PAt. REAPY'
OVERFLOW A