AD9520-0 Analog Devices, Inc., AD9520-0 Datasheet - Page 76
![no-image](/images/no-image-200.jpg)
AD9520-0
Manufacturer Part Number
AD9520-0
Description
12 Lvpecl/24 Cmos Output Clock Generator With Integrated 2.8 Ghz Vco
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9520-0.pdf
(84 pages)
Reg.
Addr
(Hex) Bit(s) Name
190
190
191
191
191
191
191
AD9520-0
Reg.
Addr
(Hex) Bit(s) Name
0F6
0F7
0F8
0F9
0FA
0FB
0FC
0FC
0FC
0FC
0FC
0FC
0FC
0FC
0FD
0FD
0FD
0FD
Table 55. LVPECL Channel Dividers
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
[7:4]
[3:0]
[7]
[6]
[5]
[4]
[3:0]
OUT6 control
OUT7 control
OUT8 control
OUT9 control
OUT10 control This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
OUT11 control This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
CSDLD En OUT7 OUT7 enabled only if CSDLD is high.
CSDLD En OUT6 OUT6 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT5 OUT5 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT4 OUT4 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT3 OUT3 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT2 OUT2 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT1 OUT1 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT0 OUT0 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En
OUT11
CSDLD En
OUT10
CSDLD En OUT9 OUT9 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT8 OUT8 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Divider 0 low cycles
Divider 0 high cycles
Divider 0 bypass
Divider 0 ignore SYNC
Divider 0 force high
Divider 0 start high
Divider 0 phase offset
Description
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
[7]
0
1
1
OUT11 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
OUT10 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
CSDLD Signal OUT7 Enable Status
0
0
1
Rev. 0 | Page 76 of 84
Not affected by CSDLD signal (default).
Asynchronous power-down.
Asynchronously enable OUT 7 if not powered down by other settings.
To use this feature, the user must use current source digital lock detect,
and set the enable LD pin comparator bit (0x01D[3]).