ST62T45B STMicroelectronics, ST62T45B Datasheet - Page 29

• Manufacturer Part Number: ST62T45B
• Description: 8-BIT OTP/EPROM MCU
• Manufacturer: STMicroelectronics

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IINTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused .
Bit 6 = LES : Level/Edge Selection bit .
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 10. Interrupt Requests and Mask Bits
GENERAL
TIMER 1
TIMER 2
A/D CONVERTER
SPI
Port PAn
Port PBn
Port PCn
32kHz OSC
7
-
Peripheral
LES
ESB
IOR
TSCR1
TSCR2
ADCR
SPI
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
32OCR
GEN
Register
-
-
C8h
D4h
D7h
D1h
C2h
C0h-C4h
C1h-C5h
C6h-CFh
DBh
Address
Register
-
0
-
GEN
ETI
EAI
ALL
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
EOSCI
Mask bit
Bit 5 = ESB: Edge Selection bit .
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt . When this
bit is set to one, all interrupts are enabled. When
this bit is cleared to zero all the interrupts (exclud-
ing NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt Sources
Interrupt
ST62E45B/T45B are summarized in theFigure 10
with associated mask bit to enable/disable the in-
terrupt request.
All Interrupts, excluding NM
TMZ: TIMER Overflow
EOC: End of Conversion
End of Transmission
PAn pin
PBn pin
PCn pin
OSCEOC
Masked Interrupt Source
sources
available
ST62T45B/E45B
I
on
All
source 3
source 4
source 1
source 2
source 2
source 2
source 3
Interrupt
source
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