CY7C4285-10ASC Cypress Semiconductor Corp, CY7C4285-10ASC Datasheet - Page 12

• Manufacturer Part Number: CY7C4285-10ASC
• Description: IC DEEP SYN FIFO 64KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4285-10ASC

• Function: Synchronous
• Memory Size: 1.1K (64 x 18)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 8ns
• Word Size: 18b
• Organization: 64Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 50mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1241

Switching Waveforms
Document #: 38-06008 Rev. *A
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Write Programmable Registers
Notes:
28. If a write is performed on this rising edge of the write clock, there will be Full
29. PAF offset = m.
30. t
D
WCLK
WCLK
rising edge of WCLK is less than t
0
SKEW3
RCLK
WEN
WEN
–D
REN
PAF
LD
17
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the
t
t
CLKH
CLKH
(continued)
FULL– M + 1 WORDS
SKEW3
t
CLK
, then PAF may not change state until the next WCLK rising edge.
t
t
ENS
ENS
t
DS
IN FIFO
PAE OFFSET
t
ENS
t
ENH
t
t
CLKL
CLKL
t
ENH
t
DH
Note 28
Note 29
PAF OFFSET
(m 1) words of the FIFO when PAF goes LOW.
t
PAF
t
ENS
t
SKEW3
FULL– M WORDS
IN FIFO
t
[30]
ENS
PAE OFFSET
D
0
[26]
– D
t
ENH
11
t
PAF synch
CY7C4275
CY7C4285
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