CY7C4211V-15AC Cypress Semiconductor Corp, CY7C4211V-15AC Datasheet - Page 2

• Manufacturer Part Number: CY7C4211V-15AC
• Description: IC SYNC FIFO MEM 512X9 32-TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4211V-15AC

• Function: Synchronous
• Memory Size: 4.6K (512 x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1212

Document #: 38-06010 Rev. *A
Selection Guide
Pin Definitions
Functional Description
The CY7C42X1V provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are program-
mable to single word granularity. The programmable flags default to
Empty-7 and Full-7.
The flags are synchronous, i.e., they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK).
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current
Density
D
Q
WEN1
WEN2/LD
Dual Mode Pin
REN1, REN2
WCLK
RCLK
EF
FF
PAE
PAF
RS
OE
Signal Name
0 8
0 8
CY7C4421V
Data Inputs
Data Outputs
Write Enable 1
Write Enable 2
Load
Read Enable
Inputs
Write Clock
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
64 x 9
Description
(continued)
CY7C4201V
256 x 9
I/O
Commercial
O Data Outputs for 9-bit bus.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
I
I
I
I
I
I
I
I
I
Data Inputs for 9-bit bus.
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is
HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Enables the device for Read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag
offset register.
programmed into the FIFO.
programmed into the FIFO.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
CY7C4211V
512 x 9
CY7C42X1V-15
66.7
15
10
11
20
4
1
CY7C4221V
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags
denoting Almost Full and Full states are updated exclusively
by WCLK. The synchronous flag architecture guarantees that
the flags maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.65m
P-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
1K x 9
CY7C4421V/4201V/4211V/4221V
CY7C42X1V-25
Description
CY7C4231V
2K x 9
40
15
25
15
20
CY7C4231V/4241V/4251V
6
1
CY7C4241V
4K x 9
CY7C42X1V-35
28.6
20
35
20
20
7
2
CY7C4251V
Page 2 of 17
8K x 9
MHz
Unit
mA
ns
ns
ns
ns
ns