BU9891GUL-W Rohm, BU9891GUL-W Datasheet - Page 10

• Manufacturer Part Number: BU9891GUL-W
• Description: WL-CSP EEPROM family Microwire Bus
• Manufacturer: Rohm

●Application
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BU9891GUL-W
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1) Method to cancel each command
2) At standby
○READ
○WRITE
○Standby current
○Timing
a：From start bit to 27 clock rise
b：27 clock rise and after
When CS is “L”, SK input is “L”, DI input is “H”, and even with middle electric potential, current does not increase.
As shown in Fig.38, when SK at standby is “H”, if CS is started, DI status may be read at the rise edge.
At standby and at power ON/OFF, when to start CS, set SK input or DI input to “L” status.
Cancel by CS=“L”
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
・Method to cancel：cancel by CS=“L”
Start bit
Start bit
1bit
CS
SK
DI
1bit
Fig.37 WRITE cancel available timing
Fig.36 READ cancel available timing
Fig.38 Wrong action timing
Cancel is available in all areas in read mode.
CS=SK=DI=”H”
Wrong recognition as a start bit
Ope code
Ope code
＊
1
2bit
2bit
Start bit input
＊
1
a
Address
Address
8bit
8bit
*1
SK
DI
・27 Rise of clock
D1
16bit
Data
16bit
Data
Enlarged figure
26
10/17
D0
27
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CS
SK
DI
*1
Note 1) If Vcc is made OFF in this area, designated address data is
Note 2) If CS is started at the same timing as that of the SK rise,
tE/W
b
Fig.39 Normal action timing
not guaranteed, therefore write once again.
write execution/cancel becomes unstable, therefore, it is
recommended to fail in SK=”L” area.
As for SK rise, necessary timing of tCSS/tCSH or higher.
If CS is started when SK=”L” or DI=”L”, a start
bit is recognized correctly.
Start bit input
Technical Note
2010.07 - Rev.A
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