FTM-9412P-F20F Fiberxon, FTM-9412P-F20F Datasheet - Page 6

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FTM-9412P-F20F

Manufacturer Part Number
FTM-9412P-F20F
Description
2x5 SFF GE-PON ONU Transceiver
Manufacturer
Fiberxon
Datasheet
2×5 SFF GE-PON ONU Transceiver
20km transmission
Recommended Interface Circuit
Figure 2 shows the recommended interface schemes.
Note A: Open emitter output internally.
Note B: LVPECL output, AC coupled internally.
.
Pin Definitions
2×5 SFF planform in Figure 3 below shows the pin information of electrical interface and mounting studs.
Functions are described in Table 6 with some accompanying notes.
P r o t o c o l
T x _ B u r s t _ C t r l
I C
R1=R2=82Ω,R3=R4=130Ω,R5=N.C
Input stage in SerDes IC is assumed with high impedance and internal bias to Vcc-1.3V
Input stage in SerDes IC is assumed without internal bias to Vcc-1.3V
R1=R2=R3=R4=N.C, R5=100Ω
R x _ S D
S e r D e s
I C
S e r D a t a
S e r D a t a
Fiberxon Proprietary and Confidential, Do Not Copy or Distribute
S e r D a t a
S e r D a t a
O u t +
O u t -
I n +
I n -
( N o t e A )
1 0 µ F
2 x 1 5 0
Figure 2 Recommended Interface Circuit
R 1
+ 3 .3 V
R 2
+ 3 .3 V
R 5
( N o t e B )
R 3
0 . 1 µ F
R 4
Figure 3 2×5 SFF Planform
1 µ H
1 µ H
1 0 µ F
Z = 5 0
Z = 5 0
Z = 5 0
Z = 5 0
0 .1 µ F
0 .1 µ F
T X _ B R S T ( 8 )
Preliminary Data Sheet
T D - ( 1 0 )
R D + ( 5 )
T D + ( 9 )
V
V
V
V
R D - ( 4 )
S D ( 3 )
C C T
C C R
E E T
E E R
( 7 )
( 6 )
( 2 )
( 1 )
V
1 0 0 n
1 0 0 n
1 0 0 n
1 0 0 n
C C R
2 x 1 5 0
4 .7 - 1 0 K
F T M - 9 4 1 2 P - F 2 0 F
1 0 0
A m p li f ie r
L i m i t in g
D r iv e r
L a s e r
Jan.27, 2005
B M
C M
3 .5 - 5 K
6

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