XRP7708 Exar Corporation, XRP7708 Datasheet - Page 22

• Manufacturer Part Number: XRP7708
• Description: Quad Channel Digital Pwm Step Down Controller
• Manufacturer: Exar Corporation

P
Each switching channel can be programmed to a phase shift of the multiples of 90 degrees [for a 4
phase configuration] or 120 degrees [for a 3 phase configuration]. Two or more of the channels
can use the same phase shift, however, it is preferable to run each channel at separate phases.
GPIO P
The General Purpose Input Output (GPIO) Pins are the basic interface between the XRP7708 and
the system. Although all of the stored data within the IC can be read back using the I
sometimes convenient to have some of those internal register to be displayed and or controlled by
a single data pin. Besides simple input output functions the GPIO pins can be configured to serve
as external clock inputs. These pins can be programmed using OTP bits or can be programmed
using the I
functions that the GPIO can be programmed to do.
NOTE: the GPIO Pins (and all I/Os) should NOT be driven without a 10K resistor when VIN is not
being applied to the IC.
The polarity of the GPIO pin can be set by using the GPIO_ACT_POL register. This register allows
any GPIO pin whether configured as an input or output to change polarity. Bits [5:0] are used to
set the polarity of GPIO 0 though 5. If the IC operates in I
[5:4] are ignored.
Each GPIO can be configured to enable a specific power rail for the system.
register allows a GPIO to enable/disable any of the following rails controlled by the chip:
When the configured GPIO is asserted externally, the corresponding rails will be enabled, and they
will be similarly disabled when the GPIO is de-asserted. This supply enabling/disabling can also be
controlled through the I
The GPIO pins can be configured as Power Good indicators for one or more rails. The GPIO pin is
asserted when all rails configured for this specific IO are within specified limits for regulation. This
information can also be found in the READ_PWRGD_SS_FLAG status register.
The GPIOs can be configured to signal Fault or Warning conditions when they occur in the chip.
Each GPIO can be configured to signal one of the following:
© 2010 Exar Corporation
GPIO Pins Polarity
Supply Rail Enable
Power Good Indicator
Fault and Warning Indication
HASE
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•
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•
•
•
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A single buck power controller
The Standby LDO
Any mix of the Standby LDO and power controller(s)
OCP Fault on Channel 1 - 4
OCP Warning on Channel 1 - 4
OVP Fault on Channel 1 - 4
UVLO Fault on VIN1 or VIN2
UVLO Warning on VIN1 or VIN2
Over Temperature Fault or Warning
S
INS
HIFT
2
C bus. This GPIO_CONFIG register allows the user close to 100 different configuration
2
C interface.
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