CS8553 Myson Technology, CS8553 Datasheet - Page 3

• Manufacturer Part Number: CS8553
• Description: TV Encoder
• Manufacturer: Myson Technology

PIN DESCRIPTION
CLK_27
VSYNC
HSYNC
P[7:0]
MD[3:0]
MASTER
CBSWAP
SVIDEO
SLEEP
FSADJUST
COMP
VREFO
VREFI/VRDAC
NC
NC
CVBS/Y
VAA
VDD
GND
AGND
VSS
Name
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
TQFP Pin No.
24-17
13-16
31,8
28
29
12
10
32
27
26
30
25
11
9
1
2
4
5
6
7
3
Pixel clock, 27MHz, twice the Y sample rate
Vertical sync, output in master mode or input in slave mode, is synchronized
by CLK.
Horizontal sync, output in master mode or input in slave mode, is
synchronized by CLK too.
YCbCr pixel inputs (TTL compatible). Also, synchronized by CLK with
respect to the incoming HSYNC timing, the higher index corresponds to a
greater significance.
Configuration inputs
in 0: slave mode, h and v sync are inputs. 1: master mode, h and v sync are
outputs.
0: normal Cr, Cb sequence. 1: swaps Cr, Cb sequence
Connected to VSS.
1: power down, reset 0: normal operation
Full scale adjust control pin. A resistor RSET is connected to GND. Used to
control the full-scale output current on analog outputs.
Compensation pin. A 0.1µF capacitor is used to bypass this pin to VCC.
Voltage reference output, typically 1.2V, may be used to connect to VREFI
input.
Voltage reference input, typically 1.235V. A 0.11µF capacitor must be used
to decouple this input to GND. DAC current switch reference input, connect
to VREFO output.
No connection
No connection
Composite output or luminance (with blanking and sync)
Analog power
Digital power
Digital ground
Analog ground
Analog ground
Description
CS8553
page 3 of 21