CS8421 Cirrus Logic, CS8421 Datasheet - Page 23
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CS8421
Manufacturer Part Number
CS8421
Description
32-bit 192 kHz Asynchronous Sample Rate Converter
Manufacturer
Cirrus Logic
Datasheet
1.CS8421.pdf
(38 pages)
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DS641F2
4.5
SDOUT/
TDM_IN
OLRCK
OSCLK
Source
OLRCK
Output
OLRCK
Clock
PCM Source 1
PCM Source 1
OSCLK
OSCLK
Reset, Power-Down, and Start-Up
When RST is low, the CS8421 enters a low-power mode, all internal states are reset, and the outputs are
disabled. After RST transitions from low to high, the part senses the resistor value on the configuration pins
(MS_SEL, SAIF, and SAOF) and sets the appropriate mode of operation. After the mode has been set (ap-
proximately 4 μ s), the part is set to normal operation and all outputs are functional.
LRCK
SCLK
SDOUT
SDOUT
TDM_IN
ILRCK
ISCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave)
CS8421
MSB
CS8421
SDOUT 4, ch A
Master
Slave
32 clks
OLRCK
SDOUT
OSCLK
SDOUT
OLRCK
OSCLK
1
1
LSB
Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)
OLRCK
OLRCK
PCM Source 2
PCM Source 2
MSB
SDOUT 4, ch B
OSCLK
OSCLK
32 clks
SDOUT
SDOUT
Figure 12. TDM Master Mode Timing Diagram
LSB
TDM_IN
ILRCK
ISCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
CS8421
CS8421
MSB
Slave
SDOUT 3, ch A
Slave
32 clks
SDOUT
OLRCK
OSCLK
2
SDOUT
OLRCK
OSCLK
2
OLRCK
LSB
OLRCK
PCM Source 3
PCM Source 3
OSCLK
MSB
OSCLK
SDOUT 3, ch B
256 OSCLKs
32 clks
SDOUT
SDOUT
TDM_IN
ILRCK
ISCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
LSB
CS8421
CS8421
Slave
MSB
Slave
SDOUT 2, ch A
OLRCK
SDOUT
OSCLK
32 clks
3
SDOUT
OLRCK
OSCLK
3
OLRCK
PCM Source 4
OLRCK
LSB
PCM Source 4
OSCLK
MSB
OSCLK
SDOUT 2, ch B
SDOUT
32 clks
SDOUT
TDM_IN
ILRCK
ISCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
CS8421
LSB
CS8421
Slave
Slave
MSB
SDOUT
SDOUT 1, ch A
OLRCK
OSCLK
4
SDOUT
www.DataSheet4U.com
32 clks
OLRCK
OSCLK
4
LSB
MSB
CS8421
SDOUT 1, ch B
32 clks
LRCK
SCLK
SDIN
LRCK
SCLK
SDIN
DSP
Slave
DSP
Slave
LSB
23