CS493002-CL Cirrus Logic, CS493002-CL Datasheet - Page 80
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CS493002-CL
Manufacturer Part Number
CS493002-CL
Description
Multi-Standard Audio Decoder Family
Manufacturer
Cirrus Logic
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12. PIN DESCRIPTIONS
VA—Analog Positive Supply: Pin 34
AGND—Analog Supply Ground: Pin 35
VD1, VD2, VD3—Digital Positive Supply: Pins 1, 12, 23
DGND1, DGND2, DGND3—Digital Supply Ground: Pins 2, 13, 24
FILT1—Phase-Locked Loop Filter: Pin 33
FILT2—Phase Locked Loop Filter: Pin 32
CLKIN—Master Clock Input: Pin 30
80
Analog positive supply for clock generator. Nominally +2.5 V.
Analog ground for clock generator PLL.
Digital positive supplies. Nominally +2.5 V.
Digital ground.
Connects to an external filter for the on-chip phase-locked loop.
Connects to an external filter for the on-chip phase-locked loop.
CS493XX clock input. When in internal clock mode (CLKSEL == DGND), this input is
connected to the internal PLL from which all internal clocks are derived. When in external
clock mode (CLKSEL == VD), this input is connected to the DSP clock. INPUT
SCDIO, SCDOUT,PSEL,GPIO9
RD,R/W,EMOE,GPIO11
WR,DS,EMWR,GPIO10
DATA7,EMAD7,GPIO7
DATA6,EMAD6,GPIO6
DATA5,EMAD5,GPIO5
DATA4,EMAD4,GPIO4
DATA3,EMAD3,GPIO3
DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1
DATA0,EMAD0,GPIO0
AUDATA3, XMT958
EXTMEM, GPIO8
ABOOT, INTREQ
A0, SCCLK
A1, SCDIN
S D A T A N 1
D G N D 1
D G N D 2
VD1
VD2
C S
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 1 44 43 42 41 40
CS493XX-CL
44-pin PLCC
Top View
39
38
37
36
35
34
33
32
31
30
29
MCLK
SCLK
LRCLK
A U D A T A 0
A U D A T A 1
A U D A T A 2
D C
D D
R E S E T
A G N D
V A
FILT1
FILT2
CLKSEL
CLKIN
CMPREQ, LRCLKN2
CMPCLK, SCLKN2
CMPDAT, SDATAN2, RCV958
LRCLKN1
SCLKN1, STCCLK2
D G N D 3
VD3
CS49300 Family DSP
DS339PP4
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