CS4270 Cirrus Logic, CS4270 Datasheet
CS4270
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... Filters This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) www.DataSheet4U.com CS4270 Analog Supply 3 Internal Voltage Reference External Mute Mute Signals Control ...
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... Integrated level translators allow easy interfacing be- tween the CS4270 and other devices operating over a wide range of logic levels. Independently addressable high-pass filters are avail- able for the right and left channel of the A/D. This allows ...
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... THERMAL CHARACTERISTICS.............................................................................................. 8 DAC ANALOG CHARACTERISTICS (CS4270-CZZ)............................................................... 9 DAC ANALOG CHARACTERISTICS (CS4270-DZZ)............................................................... 9 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 11 ADC ANALOG CHARACTERISTICS (CS4270-CZZ)............................................................. 12 ADC ANALOG CHARACTERISTICS (CS4270-DZZ)............................................................. 13 ADC ANALOG CHARACTERISTICS - ALL MODES ............................................................. 14 ADC DIGITAL FILTER CHARACTERISTICS ........................................................................ 14 DC ELECTRICAL CHARACTERISTICS ................................................................................ 15 DIGITAL CHARACTERISTICS............................................................................................... 16 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 16 SWITCHING CHARACTERISTICS - I² ...
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... Figure 10. CS4270 Typical Connection Diagram ...................................................................................... 21 Figure 11. De-Emphasis Curve ................................................................................................................. 27 Figure 12. CS4270 Recommended Analog Input Network ....................................................................... 28 Figure 13. CS5344 Example Analog Input Network .................................................................................. 29 Figure 14. CS4270 Recommended Analog Output Filter .......................................................................... 29 Figure 15. Suggested Active-Low Mute Circuit ......................................................................................... 30 Figure 16. Control Port Timing, SPI mode ................................................................................................ 31 Figure 17. Control Port Timing, I²C Mode ................................................................................................. 32 Figure 18 ...
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... Figure 53. ADC Quad-Speed Mode Transition Band (Detail) ................................................................... 47 Figure 54. ADC Quad-Speed Mode Passband Ripple .............................................................................. 47 LIST OF TABLES Table 1. Speed Modes .............................................................................................................................. 22 Table 2. Clock Ratios - Stand-Alone Mode ............................................................................................... 23 Table 3. CS4270 Stand-Alone Mode Control............................................................................................ 24 Table 4. Speed Modes .............................................................................................................................. 25 Table 5. Clock Ratios - Control Port Mode................................................................................................ 25 Table 6. Analog Input Design Parameters ................................................................................................ 28 Table 7. Memory Address Pointer............................................................................................................. 32 Table 8 ...
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... Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Character- AOUTB 23 istics specification table Pin Description CS4270 www.DataSheet4U.com MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST AD2 DS686A1 ...
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... Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris- AOUTB 23 tics specification table. DS686A1 VLC Pin Description CS4270 www.DataSheet4U.com MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST MDIV2 I²S format for the Serial Audio 7 ...
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... V IN Control Port Interface V IND-C Digital Interface V IND stg Symbol θ (Multi-layer PCB) TSSOP JA-TM θ (Multi-layer PCB) SOIC JA-SM θ (Single-layer PCB) TSSOP JA-TS θ (Single-layer PCB) SOIC JA-SS CS4270 www.DataSheet4U.com Specified Operating Conditions. Typical Min Nom Max 3.1 5.0 5.25 3.1 3.3 5.25 1.7 3.3 5.25 -10 - +70 -40 - +85 Min Typ Max -0 ...
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... DAC ANALOG CHARACTERISTICS (CS4270-CZZ) (Full-Scale Output Sine Wave, 997 Hz (Note 4 48/96/192 kHz; Test load R (see Figure 1). Measurement Bandwidth kHz, unless otherwise specified.) Parameter Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 16-Bit DAC ANALOG CHARACTERISTICS (CS4270-DZZ) (Full-Scale Output Sine Wave, 997 Hz (Note 4 48/96/192 kHz ...
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... AOUTx AGND Figure 1. Output Test Load 10 Symbol (1 kHz) 0.640•VA I OUTmax OUT 125 100 V out 2.5 3 CS4270 www.DataSheet4U.com Min Typ Max - 100 - - 0.1 0.25 -100 +100 0.688•VA 0.739• 100 - - 100 - Safe Operating Region Ω ...
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... kHz - Fs = 44.1 kHz - kHz - to -0.1 dB corner corner 0 -.05 .5770 (Note 7) 55 tgd - to -0.1 dB corner corner 0 0 0.7 (Note 7) 51 tgd - Section 11. “Appendix” on page CS4270 www.DataSheet4U.com Typ Max Unit - .4780 Fs - .4996 10/ +1.5/+ +.05/-. -.2/-.4 ...
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... ADC ANALOG CHARACTERISTICS (CS4270-CZZ) Measurement Bandwidth kHz unless otherwise specified. Input is 1 kHz sine wave. Parameter Single-Speed Mode kHz Dynamic Range Total Harmonic Distortion + Noise Double-Speed Mode kHz Dynamic Range 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise ...
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... ADC ANALOG CHARACTERISTICS (CS4270-DZZ) Measurement Bandwidth kHz unless otherwise specified. Input is 1 kHz sine wave. Parameter Single-Speed Mode kHz Dynamic Range Total Harmonic Distortion + Noise Double-Speed Mode kHz Dynamic Range 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise ...
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... CS4270 - ppm/°C Vpp - kΩ Max Unit 0.47 Fs 0.035 0.0001 deg 0.45 Fs 0.035 0.0001 deg 0.24 Fs 0.035 0.0001 deg - deg ...
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... 3 VD, VLC = VD, VLC = 3 VD, VLC = Normal Operation - Normal Operation - (Note 14) - (Note 15) PSRR VQ FILT+ CS4270 www.DataSheet4U.com Symbol Min Typ Max - - /Fs 42. See Figures 43 through 54. Typ Max - ...
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... L Symbol Single-Speed Mode Fs Double-Speed Mode Fs Quad-Speed Mode Fs Stand-Alone Mode f mclk Control Port Mode f mclk t slr t sdo t sdis t sdih t Single-Speed Mode sclkw Double-Speed Mode t sclkw Quad-Speed Mode t sclkw t slr CS4270 www.DataSheet4U.com Min Typ Max Units 0.7xVD - - 0.7xVLC - - - - 0.2xVD - - 0.2xVLC VLC - 1 1 0.4 - Min ...
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... O utput SDO UT SDIN Figure 3. Master Mode Serial Audio Port Timing LRCK Input SCLK Input SDO UT SDIN DS686A1 t sdo t sdis t sdih t slr t sdo t sdis t slr t sclkw t sdo t sdis Figure 4. Slave Mode Serial Audio Port Timing CS4270 www.DataSheet4U.com - - sdih t sdih 17 ...
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... LSB MSB - LSB MSB - I²S Figure 6. Format 24-Bit Data + CS4270 www.DataSheet4U.com Right Channel + LSB Right Channel + LSB R ight Channel + ...
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... Repeated t high sud t sust low hdd Figure 8. I²C Mode Control Port Timing www.DataSheet4U.com Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - Stop Start susp hdst t r CS4270 Unit kHz ns µs µs µs µs µs µs ns µs ns µs 19 ...
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... Figure 9. SPI Control Port Timing CS4270 www.DataSheet4U.com Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ ...
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... Settings (Control Port Ω 2 kΩ +1 using separate supplies for VA and VD, 5.1 Ω resistor not needed. See "Grounding and Power Supply Decoupling." Figure 10. CS4270 Typical Connection Diagram DS686A1 0.1 µF 1 µF 0.1 µF 1 µF 1. 5.1 Ω FILT+ AGND ...
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... Master Mode may be accessed by placing a 47 kΩ pull- the SDOUT (M/S) pin. Configuration of clock ratios in each of these modes is outlined in 5.1.3 System Clocking The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes as shown in . ...
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... The operational amplifiers in the input circuitry driving the CS4270 may generate a small DC offset into the ADC. The CS4270 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system ...
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... It is recommended that SCLK be 48x or 64x Fs to maximize system performance. Configuration of clock ratios in each of these modes will be outlined in the In Control Port Mode the CS4270 will default to Slave Mode. The user may change this default setting by changing the status of the M/S bits in the Functional Control Register (03h). ...
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... System Clocking The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes as shown in 5.2.4 Clock Ratio Selection In Control Port Master Mode, the user must configure the mode bits (M0, M1, M2) to set the speed mode and select the appropriate clock ratios. Depending on whether the CS4270 is in Master or Slave Mode, different MCLK/LRCK and SCLK/LRCK ratios may be used ...
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... ADC is routed to the input of the DAC. This mode may be activated by setting the Digital Loopback bit in the ADC & DAC Ctrl register (04h). When this bit is set, the status of the DAC_DIF(4:3) bits in register 04h will be disregarded by the CS4270. Any changes made to the DAC_DIF(4:3) bits while the Digital Loopback bit is set will have no impact on operation until the Digital Loopback bit is released, at which time the Digital Interface Format of the DAC will operate according to the format selected in the DAC_DIF(4:3) bits ...
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... One de-emphasis mode is available via the Control Port and is optimized for 44.1 kHz sampling rate. 5.2.9 Oversampling Modes The CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selec- tion is determined by the FM_&_M/S_Mode[1:0] bits in the Functional Mode register (03h). Single-Speed mode supports input sample rates kHz and uses a 128x oversampling ratio ...
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... Analog Input R1 Figure 12. CS4270 Recommended Analog Input Network Three parameters determine the values of resistors R1 and R2 as shown in attenuation, and input impedance. Source impedance is defined as the impedance as seen from the ADC looking back into the signal network. Analog performance is optimized for small source impedance and a source impedance above 2.5 kΩ ...
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... Figure 13. CS5344 Example Analog Input Network 5.4.2 Output Connections The analog output filter present in the CS4270 is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 42. The recommended external analog circuitry is shown in 3.3 µ ...
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... MCLK and LRCK must be the same for all of the CS4270’s in the sys- tem. If only one MCLK source is needed, one solution is to place one CS4270 in Master Mode, and slave all of the other CS4270’s to the one master. If multiple MCLK sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS4270 reset with the inactive edge of MCLK ...
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... SPI™ Mode In SPI mode the CS4270 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip address is 1001111. All control signals are inputs and data is clocked in on the rising edge of CCLK. ...
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... MAP will be output after the chip address. The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers ...
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... dacA dacA dacA vol<5> vol<4> vol<3> dacB dacB dacB vol<5> vol<4> vol<3> CS4270 rev<2> rev<1> Reserved PDN_DAC MCLK MCLK PopGuard freq<1> freq<0> Reserved ...
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... Power Down (Bit 0) Function: The device will enter a low-power state whenever this bit is set. The contents of the control registers are retained when the device is in power-down id<0> rev<3> Reserved Reserved CS4270 www.DataSheet4U.com rev<2> rev<1> rev<0> Reserved PDN_DAC PDN DS686A1 ...
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... FM_&_M/S_ Reserved Reserved Mode1 8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) Function: In Control Port Master Mode, the user must configure the CS4270 Speed Mode with these bits. In Control Port Slave Mode, the CS4270 auto-detects speed mode. FM_&_M/S_ FM_&_M/S_ Mode1 Mode0 ...
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... I² 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Table 10. DAC Digital Interface Formats Table 11 and may be seen in Description I² 24-bit data Table 11. ADC Digital Interface Formats CS4270 www.DataSheet4U.com Section 5.2.7 “High- Table 10 and Figures 5 through 7. Format Figure ...
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... DS686A1 invert invert ADC ch B ADC ch A 35. Table 9 on page ZeroCross Mode 0 Changes to affect immediately 1 Zero Cross enabled 0 Soft Ramp enabled 1 Soft Ramp and Zero Cross enabled (default) CS4270 www.DataSheet4U.com invert invert De-emph DAC ch B DAC ch A 35. 37 ...
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... When this bit is set, the output of the DAC for the selected channel will be muted. 38 Gain dB T1=50 µs 0dB -10dB F1 F2 3.183 kHz 10.61 kHz Figure 18. De-Emphasis Curve Mute ADC SP Mute ADC Section 5.2.6 “Auto-Mute” on page CS4270 www.DataSheet4U.com Figure µs Frequency 2 1 Mute DAC SP Mute DAC SP mute polarity 26. DS686A1 shows 0 ...
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... DS686A1 dacA dacA vol<4> vol<3> dacB dacB vol<4> vol<3> Section 8.5.2). Volume Setting 0 dB -0.5 dB -20 dB -20.5 dB -127 dB -127.5 dB Table 13. Digital Volume Control CS4270 www.DataSheet4U.com 2 1 dacA dacA vol<2> vol<1> 08h dacB dacB vol<2> vol<1> 0 dacA vol<0> 0 dacB vol<0> 39 ...
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... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. 40 CS4270 www.DataSheet4U.com DS686A1 ...
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... PLANE SIDE VIEW NOM MAX MIN -- 0.47 -- 0.004 0.006 0.05 0.035 0.04 0.80 0.012 0.19 0.386 BSC 9.60 BSC 0.256 6.30 0.177 4. 0.024 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS4270 www.DataSheet4U.com 1 E1 ∝ END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 2,3 9.70 BSC 9.80 BSC 1 6.40 6.50 4.40 4.50 1 0.65 BSC -- 0.60 0.75 4° ...
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... Figure 23. DAC Single-Speed (slow) Stopband Rejection 100 120 0.4 0.42 0.8 0.9 1 Figure 20. DAC Single-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 22. DAC Single-Speed (fast) Passband Ripple 100 120 0.8 0.9 1 0.4 0.42 Figure 24. DAC Single-Speed (slow) Transition Band CS4270 www.DataSheet4U.com 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) DS686A1 0.6 0.5 0.6 ...
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... Figure 29. DAC Double-Speed (fast) Transition Band (detail) DS686A1 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0 0.05 0.52 0.53 0.54 0.55 Figure 26. DAC Single-Speed (slow) Passband Ripple 100 120 0.4 0.42 0.8 0.9 1 Figure 28. DAC Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 30. DAC Double-Speed (fast) Passband Ripple CS4270 www.DataSheet4U.com 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.5 0.6 0.5 43 ...
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... Figure 35. DAC Quad-Speed (fast) Stopband Rejection 100 120 0.2 0.7 0.8 0.9 1 Figure 32. DAC Double-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 Figure 34. DAC Double-Speed (slow) Passband Ripple 100 120 0.7 0.8 0.9 1 0.2 Figure 36. DAC Quad-Speed (fast) Transition Band CS4270 www.DataSheet4U.com 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.35 0.8 DS686A1 ...
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... Figure 41. DAC Quad-Speed (slow) Transition Band (detail) DS686A1 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 0 0.52 0.53 0.54 0.55 Figure 38. DAC Quad-Speed (fast) Passband Ripple 100 120 0.1 0.2 0.7 0.8 0.9 1 Figure 40. DAC Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0 0.02 0.52 0.53 0.54 0.55 Figure 42. DAC Quad-Speed (slow) Passband Ripple CS4270 www.DataSheet4U.com 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 0.1 Frequency(normalized to Fs) 0.9 0.12 45 ...
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... Figure 44. ADC Single-Speed Mode Transition Band 0.10 0.08 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0.52 0.53 0.54 0.55 0.00 0.05 0.10 Figure 46. ADC Single-Speed Mode Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.43 0.45 0.7 0.8 0.9 1.0 Figure 48. ADC Double-Speed Mode Transition Band CS4270 www.DataSheet4U.com 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (normalized to Fs) 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Frequency (normalized to Fs) 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 Frequency (normalized to Fs) DS686A1 0.60 0.50 0.70 ...
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... Figure 53. ADC Quad-Speed Mode Transition Band (Detail) DS686A1 0.10 0.08 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0.50 0.53 0.55 0.00 0.05 Figure 50. ADC Double-Speed Mode Passband Ripple 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0.7 0.8 0.9 1.0 0.2 0.25 0.3 Figure 52. ADC Quad-Speed Mode Transition Band 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.45 0.5 0.55 0.6 0.00 0.05 Figure 54. ADC Quad-Speed Mode Passband Ripple CS4270 www.DataSheet4U.com 0.10 0.15 0.20 0.25 0.30 0.35 0.40 Frequency (normalized to Fs) 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 Frequency (normalized to Fs) 0.10 0.15 0.20 Frequency (normalized to Fs) 0.45 0.50 0.8 0.25 47 ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. 48 Changes Initial Advance Release www.cirrus.com CS4270 www.DataSheet4U.com DS686A1 ...