CS4192 ON Semiconductor, CS4192 Datasheet - Page 6

• Manufacturer Part Number: CS4192
• Description: Single Air-Core Gauge Driver
• Manufacturer: ON Semiconductor

microcontroller sends a 10−bit digital word into the serial
port. These 10 bits are divided as shown in Figure 4.
360 circle is divided into 1024 equal parts of 0.35 each.
Table 1 shows the data associated with the 45 divisions of
the 360 driver.
Gauge
(360 )
Input Code
To drive the gauge’s pointer to a particular angle, the
However, from a software programmers viewpoint, a
(Decimal)
1023
V
270
128
256
384
512
640
768
896
SIN−
0
MSB
D9
D9−D7 select
which octant
Table1. Nominal Output (V
Figure 4. Definition of Serial Word
D8
Figure 3. Gauge Response
Degrees
359.65
Ideal
0.748 V
135
180
225
270
315
45
90
D7
0
IV
III
Divides a 45 octant into 128 equal parts to
D6
achieve a 0.35 resolution Code 0−127
BB
V
V
360/0
Nominal
Degrees
COS+
180
135.176
180.176
225.176
270.176
315.176
359.826
COS−
D5
45.176
90.176
0.176
0.748 V
0.748 V
0.748 V
q
D4
II
BB
I
BB
D3
BB
BB
−10.476
−10.476
−10.476
10.476
10.476
10.412
−0.032
−0.032
0.032
V
= 14 V)
(V)
SIN
D2
D1
V
90
SIN+
−10.476
−10.476
−10.412
10.476
10.412
−0.032
10.476
10.476
V
0.032
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(V)
COS
LSB
D0
10
CS4192
6
first using an SPI compatible scheme. This method is shown
in Figure 5. The CS must be high and remain high for SCLK
to be enabled. Data on SI is shifted in on the rising edge of
the synchronous clock signal. Data in the shift register
changes at SO on the falling edge of SCLK. This
arrangement allows the cascading of devices. SO is always
enabled. Data shifts through without affecting the outputs
until CS is brought low. At this time the internal DAC is
updated and the outputs change accordingly.
Note the IC requires a pulse on the Chip Select (CS) pin to
clear the Status Fault (ST) after power up. OE must be high
before the falling edge of CS to enable the output buffers.
SCLK
CS
SO
V
SI
CS
OE
ST
SI
CC
The 10 bits are shifted into the device’s shift register MSB
Figure 6 shows the power−up sequence for the CS4192.
SI
(Setup)
Figure 5. Serial Data Timing Diagram
CS
Figure 6. Power Up Sequence
Setup
SI
Bits
(Hold)
10
OUTPUTS
ENABLED
SI
(tpd)
SO
10% − 90%
Bits
10
(Rise, Fall)
CS
Hold
OUTPUTS
ENABLED