MT9079 Mitel Semiconductor, MT9079 Datasheet - Page 48

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MT9079

Manufacturer Part Number
MT9079
Description
CMOS ST-BUS FAMILY Advanced Controller for E1
Manufacturer
Mitel Semiconductor
Datasheet

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MT9079
AC Electrical Characteristics - Data Link Timing
Notes:
1. The falling edge of DLCLK and IDCLK occurs on the channel 0, bit 4 to bit 3 boundary of every second ST-BUS frame.
4-284
ST-BUS Bit
Stream
C2i
C4i
DLCLK
RxFDL
ST-BUS Bit
Stream
C2i
C4i
IDCLK*
TxFDL
* This clock signal is internal to the MT9079 and cannot be accessed by the user.
1
2
3
4
Data Link Clock Output Delay
Data Link Output Delay
Data Link Setup
Data Link Hold
Characteristic
Channel 0, Bit 4
Channel 16, Bit 4
Figure 21 - Transmit Data Link Timing Diagram
Figure 20 - Receive Data Link Timing Diagram
t
DLS
Sym
Channel 0, Bit 3
Channel 16, Bit 3
t
t
t
t
t
DOD
DLH
DCD
DLS
DLH
t
t
DCD
DCD
t
DOD
Min
20
30
Typ
Channel 0, Bit 2
Channel 16, Bit 2
Max
75
75
Units
ns
ns
ns
ns
150pF, See Note 1
150pF
Conditions/Notes
V
V
V
V
TT
TT
TT,
TT
V
V
V
V
TT
TT
TT,
TT,
V
CT
V
V
CT
CT

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