NE571 Philipss, NE571 Datasheet - Page 7

• Manufacturer Part Number: NE571
• Description: Compandor
• Manufacturer: Philipss

Philips Semiconductors
VARIABLE GAIN CELL
Figure 13 is a diagram of the variable gain cell. This is a linearized
two-quadrant transconductance multiplier. Q
provide a predistorted drive signal for the gain control pair, Q
Q
output current.
The op amp maintains the base and collector of Q
potential (V
(=V
so I
current through Q
I
The op amp has thus forced a linear current swing between Q
Q
will be linear for small signals, but very non-linear for large signals,
since it is compensating for the non-linearity of the differential pair,
Q
The key to the circuit is that this same predistorted drive signal is
applied to the gain control pair, Q
pairs of transistors have the same signal applied, their collector
current ratios will be identical regardless of the magnitude of the
currents. This gives us:
1997 Aug 14
2
V
NOTE:
4
-(I
2
1
IN
Compandor
. The gain is controlled by I
by providing the proper drive to the base of Q
and Q
IN
I
C1
1
OUT
Figure 12. Rectifier Frequency Response vs Input Level
+I
/R
20k
R
=I
IN
2
2
1
)=I
) is thus forced to flow through Q
+I
140 A
2
I
IN
, under large signal conditions.
IN
I
REF
1
I
1
I 1
G
-I
Figure 13. Simplified G Cell Schematic
0
3
. Since I
IN
I
) by controlling the base of Q
IN
=I
Q
C2
2
1
is:
.
2
I
G
I 2 R 2
has been set at twice the value of I
10k
V IN
I
2
Q
280 A
FREQUENCY (Hz)
2
(= 2I
1
G
)
and a current mirror provides the
3
and Q
INPUT = 0dBm
–40dBm
–20dBm
V+
V–
1MEG
4
1
. When two differential
along with the current I
2
1
. The input current I
, Q
2
2
Q
. This drive signal
and the op amp
1
3
at ground
I
G
1
Q
, the
4
SR00687
SR00686
3
1
and
and
IN
1
,
7
other methods. A trim pin has been provided to allow trimming of the
I
I
plus the relationships I
multiplier transfer function,
I
This equation is linear and temperature-insensitive, but it assumes
ideal transistors.
If the transistors are not perfectly matched, a parabolic, non-linearity
is generated, which results in second harmonic distortion. Figure 14
gives an indication of the magnitude of the distortion caused by a
given input level and offset voltage. The distortion is linearly
proportional to the magnitude of the offset and the input level.
Saturation of the gain cell occurs at a +8dBm level. At a nominal
operating level of 0dBm, a 1mV offset will yield 0.34% of second
harmonic distortion. Most circuits are somewhat better than this,
which means our overall offsets are typically about mV. The
distortion is not affected by the magnitude of the gain control
current, and it does not increase as the gain is changed. This
second harmonic distortion could be eliminated by making perfect
transistors, but since that would be difficult, we have had to resort to
internal offsets to zero, which effectively eliminated
second harmonic distortion. Figure 15 shows the simple trim
network required.
Figure 16 shows the noise performance of the G cell. The
maximum output level before clipping occurs in the gain cell is
plotted along with the output noise in a 20kHz bandwidth. Note that
the noise drops as the gain is reduced for the first 20dB of gain
reduction. At high gains, the signal to noise ratio is 90dB, and the
total dynamic range from maximum signal to minimum noise is
110dB.
C1
C2
OUT
I
I
C4
C3
I
I
Figure 14.
G
1
I
IN
.34
I
I
4
3
2
1
1
1
To THD Trim
Figure 15. THD Trim Network
V
R
I
I
IN
2
IN
IN
G
G Cell Distortion vs Offset Voltage
I
=I
I
–6
G
1
C3
INPUT LEVEL (dBm)
200pF
+I
C4
6.2k
0
and I
OUT
V
CC
=I
3.6V
R
20k
C4
+6
-I
V
4mV
3mV
2mV
1mV
OS
C3
Product specification
will yield the
= 5mV
SA571
SR00688
SR00689