NE5560 Philipss, NE5560 Datasheet - Page 8

• Manufacturer Part Number: NE5560
• Description: Switched-mode power supply control circuit
• Manufacturer: Philipss

Philips Semiconductors
The current consumption at 12V is less than 10mA, provided that no
current is drawn from V
The Sawtooth Generator
Figure 6 shows the principal circuitry of the oscillator. A resistor
between Pin 7 and Pin 12 (GND) determines the constant current
that charges the timing capacitor C
This causes a linear increasing voltage on Pin 8 until the upper level
of 5.6V is reached. Comparator H sets the RS flip-flop and Q1
discharges C
flip-flop. During this flyback time, Q2 inhibits the output.
Synchronization at a frequency lower than the free-running
frequency is accomplished via the TTL gate on Pin 9. By activating
this gate (V
indicated in Figure 7.
Figure 8 shows a typical plot of the oscillator frequency against the
timing capacitor. The frequency range of the NE5560 goes from
<50Hz up to >100kHz.
Reference Voltage Source
The internal reference voltage source is based on the bandgap
voltage of silicon. Good design practice assures a temperature
dependency typically 100ppm/ C. The reference voltage is
connected to the positive input of the error amplifier and has a
typical value of 3.72V.
Error Amplifier Compensation
For closed-loop gains less than 40dB, it is necessary to add a
simple compensation capacitor as shown in Figures 8 and 9.
Error Amplifier with Loop-Fault Protection Circuits
This operational amplifier is of a generally used concept and has an
open-loop gain of typically 60dB. As can be seen in Figure 9, the
inverting input is connected to Pin 3 for a feedback information
proportional to V
The output goes to the PWM circuit, but is also connected to Pin 4,
so that the required gain can be set with R
indicated in Figure 9, showing the relative change of the feedback
voltage as a function of the duty cycle. Additionally, Pin 4 can be
used for phase shift networks that improve the loop stability.
When the SMPS feedback loop is interrupted, the error amplifier
would settle in the middle of its active region because of the
feedback via R
source on Pin 3 prevents this by pushing the input voltage high via
1994 Aug 31
Switched-mode power supply control circuit
9
<2V), the setting of the sawtooth is prevented. This is
(8-12)
(3-4)
O
.
down to 1.1V, where comparator L resets the
. This would result in a large duty cycle. A current
Z
and R
V
Z
R
(7-12)
7
T
(8-12)
C
20k .
T
8
.
S
and R
5.6V
1.1V
(3-4)
–
+
–
+
N
L
. This is
Figure 6. Sawtooth Generator
9 SYN
SET
RESET
8
the voltage drop over R
zero, provided that R
short-circuited, the duty cycle would jump to the adjusted maximum
duty cycle. Therefore, an additional comparator is active for
feedback voltages at Pin 3 below 0.6V. Now an internal resistor of
typically 1k is shunted to the impedance on the
Depending on this impedance, will be reduced to a value
will be discussed further.
The Pulse-Width Modulator
The function of the PWM circuit is to translate a feedback voltage
into a periodical pulse of which the duty cycle depends on that
feedback voltage. As can be seen in Figure 10, the PWM circuit in
the NE5560 is a long-tailed pair in which the sawtooth on Pin 8 is
compared with the LOWEST voltage on either Pin 4 (error amplifier),
Pin 5, or Pin 6 (
Figure 11. The output of the PWM causes the resetting of the output
bi-stable.
Limitation of the Maximum Duty Cycle
With Pins 5 and 6 not connected and with a rather low feedback
voltage on Pin 3, the NE5560 will deliver output pulses with a duty
cycle of
cause problems. Especially in forward converters, where the
transformer will saturate when exceeds 50%, a limitation of the
maximum duty cycle is a must.
A DC voltage applied to Pin 6 (PWM input) will set
in accordance with Figure 11. For low tolerances of
voltage on Pin 6 should be set with a resistor divider from V
The upper and lower sawtooth levels are also set by means of an
internal resistor divider from V
with the
compensated and the sawtooth levels are determined by internal
resistor matching rather than by absolute resistor tolerance. Figure
12 can be used for determining the tap on the bleeder for a certain
As already mentioned, Figure 13 gives a graphical representation of
this. The value o is limited to the lower and the higher side;
MAX
It must be large enough to ensure that at maximum load and mini-
mum input voltage the resulting feedback voltage on Pin 3
exceeds 0.6V.
It must be small enough to limit the amount of energy in the SMPS
when a loop fault occurs. In practice, a value of 10-15% will be a
good compromise.
setting.
MAX
95%. In many SMPS applications, however, this high will
setting is low because tolerances in V
MAX
Q1
(3-4)
and slow-start). The transfer graph is given in
(3-4)
>100k. When the feedback loop is
TO OUTPUT LATCH
. As a result, the duty cycle will become
Q2
Z
, so forming a bridge configuration
TO PWM
NE/SE5560
Product specification
MAX
MAX
Z
MAX
setting Pin 6.
are
at a value
, this
Z
SL00365
0
. This
(Pin 2).