SKY73112 Skyworks Solutions, SKY73112 Datasheet - Page 4

• Manufacturer Part Number: SKY73112
• Description: High Performance VCO/Synthesizer
• Manufacturer: Skyworks Solutions

PRELIMINARY DATA SHEET • SKY73112 VCO/SYNTHESIZER
Table 2. CLK, DATA, LE Preset Timing Parameters
VCO MFD Block
The MFD block divides down the prescaler output to the Phase
Locked Loop (PLL) reference frequency. A third order cascaded
Σ∆ modulation technique minimizes spurs through randomization
of the division ratio.
The MFD block controls the division ratio by dynamically
programming the M and A counters in the N-counter.
Phase Detector and Charge Pump
The phase detector and charge pump detect and integrate the
phase and frequency errors of the divided down VCO output
versus the reference clock. This results in a feedback adjustment
of the control voltage for the VCO.
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Input high voltage (V
Input low voltage (V
Input current (l
Clock frequency
Clock high (t
Clock low (t
Data set up (t
Data hold (t
Clock to latch enable (t
Latch enable width (t
Latch enable to clock (t
Word length
Number of words
Current drain
(Words 0-3, bits [25:0])
Power-On
CKL
DHD
CKH
Preset
DSU
DATA
)
DIG
)
CLK
)
July 9, 2007 • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • 200736A
LE
)
)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
IL
IH
)
LEW
)
CLE
LEC
)
)
)
Register
(Register Address,
Load
2 LSB Decode
Words 0-3
Bits [1:0]
Bits [1:0])
Bits [25:2]
Parameter
Latch
Operation
Register
Mode
Figure 4. Serial Bus Block Diagram
Word 0
Bits [25:2]
Calibration
Latch
Register
Control
Auto
Lock Detect
Lock detection circuitry provides a CMOS logic level indication
when the PLL is frequency locked (high when locked).
Reference Input Divider
The R-counter (reference input clock divider) consists of three
divide-by-two blocks and one multiplexer controlled by the
RDIV[1:0] parameter in Legacy Word 2. The R-counter is used to
select a divide-by-one to a divide-by-eight function.
1.6 V
0.3 V
1 µA (maximum)
15 MHz (maximum)
15 ns (minimum)
15 ns (minimum)
20 ns (minimum)
10 ns (minimum)
20 ns (minimum)
15 ns (minimum)
15 ns (minimum)
26 bits
4
2 µA
Word 1
Bits [25:2]
Frequency
Control 1
Latch
Register
Value
Word 2
Bits [25:2]
Frequency
Control 2
Register
Latch
Word 3
Bits [25:2]
S918