SKY73101 Skyworks Solutions, SKY73101 Datasheet - Page 4

• Manufacturer Part Number: SKY73101
• Description: High Performance VCO/Synthesizer
• Manufacturer: Skyworks Solutions

PRELIMINARY DATA SHEET • SKY73101 VCO/SYNTHESIZER
Table 2. CLK, DATA, LE Preset Timing Parameters
VCO Prescalers
The VCO prescalers divide the VCO output signal by either 16/17
or 8/9. The Σ∆ modulator determines whether to divide by 16 or
17 in the 16/17 mode, or whether to divide by 8 or 9 in the 8/9
mode.
N-Counter
The N-counter consists of two asynchronous ripple counters, a
6-bit M-counter and a 4-bit A-counter. The M-counter determines
the counts using the lower division ratio in the prescaler (8 or 16);
the A-counter determines the counts using the upper division ratio
(9 or 17).
By changing the counter setting at each reference clock cycle, the
Modulated Fractional Divider (MFD) achieves the desired noise
shaping.
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Input high voltage (V
Input low voltage (V
Input current (l
Clock frequency
Clock high (t
Clock low (t
Data set up (t
Data hold (t
Clock to latch enable (t
Latch enable width (t
Latch enable to clock (t
Word length
Number of words
Current drain
(Words 0-3, bits [25:0])
Power-On
CKL
DHD
CKH
Preset
DSU
DATA
)
June 20, 2007 • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • 200724A
DIG
)
CLK
)
LE
)
)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
IL
IH
)
LEW
)
CLE
LEC
)
)
)
Register
(Register Address,
Load
2 LSB Decode
Words 0-3
Bits [1:0]
Bits [1:0])
Bits [25:2]
Parameter
Latch
Operation
Register
Mode
Figure 4. Serial Bus Block Diagram
Word 0
Bits [25:2]
Calibration
Latch
Register
Control
Auto
VCO MFD Block
The MFD block divides down the prescaler output to the Phase
Locked Loop (PLL) reference frequency. A third order cascaded
Σ∆ modulation technique minimizes spurs through randomization
of the division ratio.
The MFD block controls the division ratio by dynamically
programming the M and A counters in the N-counter.
Phase Detector and Charge Pump
The phase detector and charge pump detect and integrate the
phase and frequency errors of the divided down VCO output
versus the reference clock. This results in a feedback adjustment
of the control voltage for the VCO.
1.6 V
0.3 V
1 µA (maximum)
15 MHz (maximum)
15 ns (minimum)
15 ns (minimum)
20 ns (minimum)
10 ns (minimum)
20 ns (minimum)
15 ns (minimum)
15 ns (minimum)
26 bits
4
2 µA
Word 1
Bits [25:2]
Frequency
Control 1
Latch
Register
Value
Word 2
Bits [25:2]
Frequency
Control 2
Register
Latch
Word 3
Bits [25:2]
S918