SKY73100 Skyworks Solutions, SKY73100 Datasheet - Page 5

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SKY73100

Manufacturer Part Number
SKY73100
Description
High Performance VCO/Synthesizer
Manufacturer
Skyworks Solutions
Datasheet

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Lock Detect
Lock detection circuitry provides a CMOS logic level indication
when the PLL is frequency locked (high when locked).
Reference Input Divider
The R-counter (reference input clock divider) consists of three
divide-by-two blocks and one multiplexer controlled by the
RDIV[1:0] parameter in Legacy Word 2. The R-counter is used to
select a divide-by-one to a divide-by-eight function.
Synthesizer Output Switch
An on-chip switch is integrated into the SKY73100 RF output after
the balun and is controlled by the SW_EN signal (pin 4) as
indicated below:
The switch provides >50 dB isolation at the synthesizer RF
output. This allows the SKY73100 to be used for GSM
applications.
Synthesizer Programming
To program the synthesizer to the correct frequency, values for
the N-counter (both M and A portions), fractional divisor (FN), and
fractional modulus extender (ME) are needed. These values are
used to determine the total divider ratio, D
Equation 1:
Where: N
Because of the way the ∆Σ modulator is implemented in the
SKY73103, the number 3.5 must be added to the division number
to obtain the final division ratio.
The calculated value for D
correct synthesizer frequency, RF:
Where: F
The 6-bit M-counter and the 4-bit A-counter portions of the N-
counter are calculated according to the following relationships:
N
(D
actual
www.DataSheet4U.com
Total
– 3.5):
is the actual N-counter value and is the integer portion of
FN
ME
R1 = the reference divider radio
REF
actual
actual
SW_EN Input
actual
= the reference frequency
= the actual value of the N-counter
200361A • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • June 20, 2007
D
High
Low
= the actual fractional divisor
= the actual fractional modulus extender
Total
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
= N
actual
RF
Total
+ FN
=
can then be used to determine the
F
R1
REF
actual
×
+ ME
D
Total
Synthesizer Output
actual
Total
, according to
+ 3.5
On
Off
(1)
(2)
If:
Then: N = M
Where: N is the number to be programmed into the N-counter.
The synthesizer has a selectable prescaler of 8/9 or 16/17. If the
16/17 prescaler is used:
In this case, N is the same as N
N
If the 8/9 prescaler is used:
Here, N is not equal to N
three LSBs (the 4
The fractional divisor code (FN) sets the fractional-N modulo up to
256 modulo according to the following equation:
The value of FN is equal to the binary representation of 256 (or 2
× FN
The fractional modulo can be extended up to 2
extender (ME) if required:
The value of ME is equal to the binary representation of the
integer part of 2
Example 1:
A desired synthesizer frequency of 2640.45 MHz is required using
a crystal frequency of 16 MHz and a 16/17 prescaler. Since the
maximum internal reference frequency is 25 MHz, the crystal
frequency does not need to be divided. However, a reference
divider ratio of 2 is used for this example.
Restating Equation 2 as a function of D
Where: RF = 2640.45
Determine N
fractional portion:
actual
ME
actual
, and A is equal to the four LSBs of N
actual
FN
M = M
A = A
, or:
PRELIMINARY DATA SHEET • SKY73100 VCO/SYNTHESIZER
actual
P = 2
P = 8
ME = D
R1 = 2
F
= D
REF
FN = D
actual
actual
D
= 16
actual
×
=
14
Total
4
(1/2
D
23
2
= 16
by subtracting 3.5 from D
(binary number, fit to four bits)
th
7
14
4
(binary number, fit to six bits)
× ME
⎜ ⎜
bit of the A-counter is a “don’t care” bit).
+ A
= (2640.45
7
×
1
2
9
N
) + D
×
⎟ ⎟
actual
2
+
2
14
actual
actual
7
D
+ D
13
+ D
= M
6
, or:
⎜ ⎜
(1/2
. The A-counter portion only uses the
2
13
1
6
2
actual
×
10
×
×
⎟ ⎟
actual
) + D
+
2
2
2)/16 = 330.05625
6
×
D
13
, M is equal to the six MSBs of
+ D
5
P + A
+ D
⎜ ⎜
12
2
Total
1
(1/2
3
5
12
×
⎟ ⎟
:
actual
actual
Total
+
×
2
11
5
) + . . . + D
2
+ . . . D
.
and removing the
12
23
+ . . .D
using the modulo
+
D
0
0
⎜ ⎜
0
2
0
1
(1/2
8
⎟ ⎟
23
)
(3)
(4)
8
)
5

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