HMP9701A Intersil Corporation, HMP9701A Datasheet
HMP9701A
Related parts for HMP9701A
HMP9701A Summary of contents
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... HMP9701A helps pave the way for PC’97 compliant desktop, portable and entertainment PCs with a cost effective high-quality audio solution. As the analog front end of the AC’97 chipset, the HMP9701A accepts line level audio inputs from seven different sources and converts the analog audio to 16-bit digital streams of either ste- reo or mono data. The 48 kss data is transmitted to the control- ler via the AC’ ...
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... PC_BEEP STEREO SIGNAL PATH MONO SIGNAL PATH Functional Description The HMP9701A is a full-duplex stereo audio codec compliant to the AC’97 Codec specification. This component is designed for use in multimedia and business personal computers. The codec includes full duplex stereo converters, a mic pass through ADC, complete on-chip anti-alias fi ...
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... CONTROLLER FIGURE 1. HMP9701A CONNECTION TO AC’97 CONTROLLER Digital Serial Interface (AC Link) The HMP9701A is linked to an AC’97 digital controller via a 5 pin digital serial interface as shown in Figure 1. This inter- face, the AC-link, supports bidirectional, fixed rate, serial data streams. The data transfers are based on a time divi- ...
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... A “1” given bit position of Slot 0 indi- cates that the corresponding time slot within the audio frame contains valid data. If the HMP9701A “tags” a slot invalid, it will set the data bits comprising that slot to zero. AC Link Output Frame (SDATA_OUT) The audio output frame contains data targeted for the HMP9701A’ ...
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... FIGURE 5. START OF AUDIO INPUT FRAME The first bit of an input audio frame (Slot 0, bit 15) indicates whether the HMP970’s AC Link is functional. If the “Codec Ready” bit the HMP9701A is not ready for normal COMMENT operation. If the “Codec Ready” bit is “1”, the HMP9701A is ready to perform control and status register transfers ...
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... HMP9701A. A summary of the power down com- mands is given in Table 10 with a more complete description given in the Control Register Section. Note, the HMP9701A is a fully static design which will preserve the contents of the inter- nal control registers if the internal clock is stopped. ...
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... By driving RESET low, BIT_CLK will be activated, the AC-Link will return to normal operation, and all HMP9701A control registers will be initialized to their default values. RESET is an asynchronous HMP9701A input. Note: the HMP9701A will remain in the reset state as long as RESET is asserted “low”. HMP9701A Suggested Powerdown Sequences ...
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... Testability The HMP9701A provides a test mode to support the in cir- cuit test capabilities provided by automatic test equipment (ATE). In this mode, the HMP9701A drives its digital AC-Link outputs (BIT_CLK and SDATA_IN high impedance state. This allows for in circuit testing of the digital controller component of the sound subsystem ...
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... Internal Clock Disable (1 = CLK Off CLK On) Default: na The lower byte of this register is used to monitor the status of individual sections with in the HMP9701A. The status bits, as summarized in Table 19, indicate whether a subsection is in it’s normal operational state (Ready). Note: the status bits are read only, and writes to this register will have no effect on the state of these bits ...
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REG NAME D15 D14 D13 00h Reset 02h Master Volume Mute X ML5 04h Reserved 06h Master Volume Mono Mute X X 08h Reserved 0Ah PC_BEEP Volume Mute X X 0Ch ...
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... NUMBER OUTPUT DIGITAL I/O RESET 11 I RESET - This active low signal causes a HMP9701A hardware reset that will return the control/sta- tus registers to their default conditions. SYNC 10 I SYNC - 48kHz sync pulse which defines the beginning of serial audio I/O frames. Note: must be synchronous to BIT_CLK. ...
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... Crystal Output. Leave this pin unconnected when using an external clock source Analog Supply Voltage (5.0V). AA AGND 26 Analog Ground Digital Supply Voltage (5.0V). DD GND Digital Ground. Reserved 33,39 These pins should NOT be connected externally to any device. They must be left floating! HMP9701A DESCRIPTION 12 ...
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... Operating Conditions Temperature Range HMP9701ACN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... TEST CONDITION Note CRL t R2BC t SRH t S2BC t PDWN t SU2RST t Note 2 HZ MIN TYP 0 - 0.4xFs - - - 0.6xFs - MIN TYP - 0.02 - 0.02 14 HMP9701ACN MIN TYP MAX UNITS - 48 - kHz - 20 BCP - 240 * BCP 1 BCP - 1 ...
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... Master Volume Span for LINE_OUT, MONO_OUT (0dB to -46.5dB) Master Volume Step Size Mixer Input Gain Span for LINE_IN, CD, VIDEO, AUX, PHONE, MIC (+12dB to -34.5dB) Mixer Input Gain Step SIze PC_BEEP Attenuation Span (0dB to 45dB) PC_BEEP Attenuation Step Size HMP9701A MIN TYP - 80 - ...
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... Based on 1kHz, Full scale analog tone input; Measurement Bandwidth 20kHz, A-weighted. 4. DAC’s driven with 1kHz, Full Scale PCM Sine Wave, output measurement bandwidth 20kHz, A-weighted. 5. Test performed with C = 40pF 4mA This is measured relative to a nominal output level. HMP9701A MIN TYP - 2.83 10 ...
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... FREQUENCY (xF FIGURE 12. ANALOG-TO-DIGITAL TRANSITION BAND FREQUENCY RESPONSE (FULL SCALE LINE INPUTS, 0dB) 0.05 0 -0.05 -0.10 -0.15 -0.20 FREQUENCY (xF FIGURE 14. DIGITAL-TO-ANALOG PASSBAND FREQUENCY RESPONSE (FULL SCALE INPUTS, 0dB) HMP9701A 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -0.18 -0 FIGURE 11. ANALOG-TO-DIGITAL PASSBAND FREQUENCY RESPONSE (FULL SCALE LINE INPUTS, 0dB) ...
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... SRH SYNC BIT_CLK FIGURE 18. WARM RESET TIMING t t BCH BIT_CLK t SH SYNC FIGURE 20. CLOCKS BIT_CLK SDATA_IN SDATA_OUT SYNC HMP9701A RESET SDATA_OUT BIT_CLK, SDATA_IN BIT_CLK, SDATA_IN FIGURE 19. RISE AND FALL TIMES BCL BIT_CLK SDATA_IN SLOT SDATA_OUT SLOT 12 NOTE: BCLK not to scale. ...
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... HMP9701A HMP9701A XTL_IN 2 LINE_OUT_R XTL_OUT 3 LINE_OUT_L GND 4 SDATA_OUT Reserved 5 BIT_CLK 6 AFILT3 GND 7 AFILT2 SDATA_IN AFILT1 OUT VREF 9 VREF SYNC 10 AGND RESET AA 11 PC_BEEP ...
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... Locate all decoupling capacitors CLOSE to their associat- ed pins on the codec. HMP9701A 5. Please note that all analog inputs and outputs of the HMP9701A codec are at the DC level of V quire AC coupling to zero biased signal sources and destinations. 6. Keep all analog input and output traces as short as possible, prevent any coupling from adjacent digital lines ...