HMP8170CN Intersil Corporation, HMP8170CN Datasheet - Page 14

• Manufacturer Part Number: HMP8170CN
• Description: NTSC/PAL Video Encoder
• Manufacturer: Intersil Corporation

Composite + YUV Output Mode
The HMP8172/HMP8173 also provide composite with
component YUV output mode. When analog YUV video is
selected, the HMP817x scales the filtered YCbCr data to
match the levels required by its DACs. During the scaling,
values less than 16 are clamped to 16. The scaling factors
for Cb and Cr are the same, but the CbCr scaling factor is
different from the Y scaling factor. The encoder uses
different sets of scale factors for NTSC and PAL to
accommodate their different black levels.
The analog YUV outputs have a range of 0.3-1.0V with an
optional blanking pedestal. Composite sync information
(0.0-0.3V) may be optionally added to the Y output. VBI data
is included on the Y output. The HMP817x also generates
composite video when in YUV output mode. All four outputs
are time aligned. The output pin assignments are
summarized in Table 12.
Power Down Modes
To reduce power dissipation, any of the four output DACs
may be turned off. Each DAC has an independent enable bit.
Each output may be disabled in the host control register.
When the power down mode is enabled, all of the DACs and
internal voltage reference are powered down (forcing their
outputs to zero) and the data pipeline registers are disabled.
The host processor may still read from and write to the
internal control registers.
Host Interfaces
Reset
The HMP817x resets to its default operating mode on power
up, when the reset pin is asserted for at least four CLK
cycles, or when the software reset bit of the host control
register is set. During the reset cycle, the encoder returns its
internal registers to their reset state and deactivates the I
interface.
I
The HMP817x provides a standard I
supports fast-mode (up to 400Kbps) transfers. The device
acts as a slave for receiving and transmitting data only. It will
not respond to general calls or initiate a transfer. The
encoder’s slave address is either 0100 000x
input pin is low or 0100 001x
the address is the I
The I
the interface is not active, SCL and SDA must be pulled high
using external 4-6k pull-up resistors. The I
data timing is shown in Figures 10 and 11.
During I
address specifies the sub address, and is written into the
address register. Only the seven LSBs of the subaddress are
used; the MSB is ignored. Any remaining data bytes in the
2
C Interface
2
C interface consists of the SDA and SCL pins. When
2
C write cycles, the first data byte after the slave
2
C read flag.)
B
14
when it is high. (The ‘x’ bit in
HMP8170, HMP8171, HMP8172, HMP8173
2
C interface and
B
2
C clock and
when the SA
2
C
I
with the register specified by the address register. The 7-bit
address register is incremented after each data byte in the
I
or reserved registers is ignored.
During I
specified by the address register is output. The address
register is incremented after each data byte in the I
cycle. Reserved bits within registers return a value of “0”.
Reserved registers return a value of 00
The HMP817x’s operating modes are determined by the
contents of its internal registers which are accessed via the
I
the host processor at any time. However, some of the bits
and words are read only or reserved and data written to
these bits is ignored.
Table 13 lists the HMP817x’s internal registers. Their bit
descriptions are listed in Tables 14 through 45.
2
2
2
C write cycle are written to the control registers, beginning
C write cycle. Data written to reserved bits within registers
C interface. All internal registers may be written or read by
SUB ADDRESS
(HEX)
08-0D
1A-1F
6B-6F
28-2F
30-6A
70-7F
2
00
01
02
03
04
05
06
07
0E
0F
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
C read cycles, data from the control register
TABLE 13. CONTROL REGISTER NAMES
CONTROL REGISTER
start h_blank high
start v_blank high
video processing
start h_blank low
start v_blank low
phase increment
VBI data enable
test and unused
test and unused
VBI data input
caption_284A
caption_284B
output format
host control 1
host control 2
field control 1
field control 2
caption_21A
caption_21B
end h_blank
end v_blank
input format
WSS_283A
WSS_283B
timing I/O 1
timing I/O 2
product ID
WSS_20A
WSS_20B
CRC_283
reserved
CRC_20
reserved
reserved
H
.
CONDITION
RESET
2
1E
4A
7A
00
06
80
00
00
00
00
00
80
80
80
80
00
00
00
00
3F
3F
03
03
01
13
00
00
C read
-
-
-
-
-
-
-
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H